Tohru Ishihara
Orcid: 0000-0002-1650-9958
According to our database1,
Tohru Ishihara
authored at least 116 papers
between 1993 and 2024.
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Bibliography
2024
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024
2023
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2022
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the International Conference on Rebooting Computing, 2020
2019
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing.
Integr., 2019
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
IEICE Trans. Electron., 2019
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator.
Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
J. Low Power Electron., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
2017
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
An integrated optical parallel adder as a first step towards light speed data processing.
Proceedings of the International SoC Design Conference, 2016
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring.
IEEE J. Solid State Circuits, 2015
IPSJ Trans. Syst. LSI Des. Methodol., 2015
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
An impact of process variation on supply voltage dependence of logic path delay variation.
Proceedings of the VLSI Design, Automation and Test, 2015
An energy-efficient on-chip memory structure for variability-aware near-threshold operation.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Microarchitectural-level statistical timing models for near-threshold circuit design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
2013
ACM Trans. Embed. Comput. Syst., 2013
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
DC-DC Converter-Aware Task Scheduling and Dynamic Reconfiguration for Energy Harvesting Embedded Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
J. Electr. Comput. Eng., 2012
A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems.
Proceedings of the SMARTGREENS 2012 - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems, Porto, Portugal, 19, 2012
A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems.
Proceedings of the SMARTGREENS 2012 - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems, Porto, Portugal, 19, 2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
A flexible structure of standard cell and its optimization method for near-threshold voltage operation.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
I/O aware task scheduling for energy harvesting embedded systems with PV and capacitor arrays.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
2011
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies.
Trans. High Perform. Embed. Archit. Compil., 2011
Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
An integrated optimization framework for reducing the energy consumption of embedded real-time applications.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
J. Signal Process. Syst., 2010
SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems.
Proceedings of the 2010 International Conference on Compilers, 2010
2009
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion.
IPSJ Trans. Syst. LSI Des. Methodol., 2009
IPSJ Trans. Syst. LSI Des. Methodol., 2009
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009
2008
A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die V<sub>th</sub> variation.
Microelectron. J., 2008
IEICE Trans. Electron., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Electron. Express, 2008
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Simultaneous optimization of memory configuration and code allocation for low power embedded systems.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008
2007
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems.
IEICE Trans. Electron., 2007
Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006
2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Energy-Efficient Embedded System Design at 90nm and Below - A System-Level Perspective -.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
A cache-defect-aware code placement algorithm for improving the performance of processors.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors.
Proceedings of the 2005 Design, 2005
2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2001
IEEE Des. Test Comput., 2001
A system level memory power optimization technique using multiple supply and threshold voltages.
Proceedings of ASP-DAC 2001, 2001
2000
Des. Autom. Embed. Syst., 2000
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors.
Proceedings of the 2000 Design, 2000
1999
Proceedings of the 12th International Symposium on System Synthesis, 1999
Way-predicting set-associative cache for high performance and low energy consumption.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 1998 Design, 1998
Proceedings of the ASP-DAC '98, 1998
1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1993