Tohru Adachi

According to our database, Tohru Adachi authored at least 6 papers between 1982 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

MN-Core - A Highly Efficient and Scalable Approach to Deep Learning.

Ken Namura, Johannes Maximilian Kühn, Tohru Adachi, H. Imachi, H. Kaneko, T. Kato, Go Watanabe, Naoto Tanaka, S. Kashihara, Hiroshi Miyashita, Y. Tomonaga, Ryosuke Okuta, Takuya Akiba, Brian Vogel, S. Kitajo, F. Osawa, K. Takahashi, Y. Takatsukasa, K. Mizumaru, T. Yamauchi, J. Ono, A. Takahashi, Tanvir Ahmed, Y. Doi, K. Hiraki, J. Makino

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

1988

Software Environment for 500 MHz VLSI Test System "ULTIMATE".

Tohru Adachi, M. Tanno, Tsuneta Sudo

Proceedings of the Proceedings International Test Conference 1988, 1988

1987

Top-Down Layout for Hierarchical Custom Design.

Kazuhiro Ueda, Hitoshi Kitazawa, Tohru Adachi, Ikuo Harada

IEEE Des. Test, 1987

1986

An automatic cell pattern generation system for CMOS transistor-pair array LSI.

Hiroshi Miyashita, Tohru Adachi, Kazuhiro Ueda

Integr., 1986

1985

An Integrated Design Automation System for VLSI Circuits.

Osamu Karatsu, Tamio Hoshino, Makoto Endo, Hitoshi Kitazawa, Tohru Adachi, Kazuhiro Ueda

IEEE Des. Test, 1985

1982

Hierarchical top-down layout design method for VLSI chip.

Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo

Proceedings of the 19th Design Automation Conference, 1982