Tobias Bjerregaard

According to our database1, Tobias Bjerregaard authored at least 13 papers between 2004 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2014
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2012
Quest for the ultimate network-on-chip: the NaNoC project.
Proceedings of the 2012 Interconnection Network Architecture, 2012

2007
A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Hardware compilation of application-specific memory-access interconnect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A survey of research and practices of Network-on-chip.
ACM Comput. Surv., 2006

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Packetizing OCP Transactions in the MANGO Network-on-Chip.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip.
Proceedings of the 2005 Design, 2005

SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.
Proceedings of the Integrated Circuit and System Design, 2004


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