To-Po Wang

Orcid: 0000-0003-4696-2259

According to our database1, To-Po Wang authored at least 11 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
Design and Analysis of Simultaneous Wideband Input/Output Matching Technique for Ultra-Wideband Amplifier.
IEEE Access, 2021

2017
Fast and Accurate Frequency-Dependent Behavioral Model of Bonding Wires.
IEEE Trans. Ind. Informatics, 2017

2015
Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A high-gain low-power low-noise-figure differential CMOS LNA with 33% current-reused negative-conductance accommodation structure.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014
Significant Reduction of Electromagnetic Interference for Fine-Motion Control Rod Drive in a Nuclear Reactor.
IEEE Trans. Ind. Electron., 2014

An 82.3- to 87.4-GHz modified differential Colpitts VCO in 0.18-µm CMOS.
IEICE Electron. Express, 2014

A new dual -<i>G</i><sub>m</sub> structure with Class-AB operation of low-power low-phase-noise K-band CMOS VCO.
IEICE Electron. Express, 2014

2012
A 0.4-V 1.08-mW 12-GHz high-performance VCO in 0.18-µm CMOS.
Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012

2011
A CMOS Colpitts VCO Using Negative-Conductance Boosted Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A low-power low-phase-noise wide-tuning-range K-band VCO in 0.18-µm CMOS.
IEICE Electron. Express, 2011

Performance enhancement techniques for CMOS power amplifier.
IEICE Electron. Express, 2011


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