Tiziano Villa

Inf. Comput., 2024

Enhancing Safety and Privacy in Industry 4.0: The ICE Laboratory Case Study.

[BibT_eX]

[DOI]

IEEE Access, 2024

Dependability Evaluation of Industrial Networks by Using Monte Carlo With Importance Sampling.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Emerging Technologies and Factory Automation, 2024

2023

Rigorous Function Calculi in Ariadne.

[BibT_eX]

[DOI]

Pieter Collins

CoRR, 2023

Generation of synchronizing state machines from a transition system: A region-based approach.

[BibT_eX]

[DOI]

Int. J. Appl. Math. Comput. Sci., 2023

Seto: A Framework for the Decomposition of Petri Nets and Transition Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package.

[BibT_eX]

[DOI]

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022

Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis.

[BibT_eX]

[DOI]

Anna Bernasconi

Valentina Ciriani

IEEE Trans. Computers, 2022

Dynamic controllability of temporal networks with instantaneous reaction.

[BibT_eX]

[DOI]

Inf. Sci., 2022

Special issue: Formal verification of cyber-physical systems.

[BibT_eX]

[DOI]

Inf. Comput., 2022

Automating Numerical Parameters Along the Evolution of a Nonlinear System.

[BibT_eX]

[DOI]

Proceedings of the Runtime Verification - 22nd International Conference, 2022

Process-driven Collision Prediction in Human-Robot Work Environments.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022

Decomposition of transition systems into sets of synchronizing Free-choice Petri Nets.

[BibT_eX]

[DOI]

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Dynamic Controllability of Temporal Networks via Supervisory Control.

[BibT_eX]

[DOI]

Proceedings of the Short Paper Proceedings of the 4th Workshop on Artificial Intelligence and Formal Verification, 2022

2021

Mining CSTNUDs significant for a set of traces is polynomial.

[BibT_eX]

[DOI]

Guido Sciavicco

Inf. Comput., 2021

Equivalence checking and intersection of deterministic timed finite state machines.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2021

Mining Temporal Networks: Results and Open Problems.

[BibT_eX]

[DOI]

Guido Sciavicco

Proceedings of the 3rd Workshop on Artificial Intelligence and Formal Verification, 2021

Decomposition of transition systems into sets of synchronizing state machines.

[BibT_eX]

[DOI]

Padmanabhan Balasubramanian

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

A Boolean Heuristic for Disjoint SOP Synthesis.

[BibT_eX]

[DOI]

Anna Bernasconi

Valentina Ciriani

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020

The Quotient in Preorder Theories.

[BibT_eX]

[DOI]

Íñigo X. Íncer Romeo

Leonardo Mangeruca

Proceedings of the Proceedings 11th International Symposium on Games, 2020

Higher Order Method for Differential Inclusions.

[BibT_eX]

[DOI]

CoRR, 2020

Mining Significant Temporal Networks Is Polynomial.

[BibT_eX]

[DOI]

Guido Sciavicco

Proceedings of the 27th International Symposium on Temporal Representation and Reasoning, 2020

A computable and compositional semantics for hybrid automata.

[BibT_eX]

[DOI]

Proceedings of the HSCC '20: 23rd ACM International Conference on Hybrid Systems: Computation and Control, 2020

Computing the full quotient in bi-decomposition by approximation.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

On the Complexity of Resource Controllability in Business Process Management.

[BibT_eX]

[DOI]

Proceedings of the Business Process Management Workshops, 2020

Dynamic Controllability and (J, K)-Resiliency in Generalized Constraint Networks with Uncertainty.

[BibT_eX]

[DOI]

Proceedings of the Thirtieth International Conference on Automated Planning and Scheduling, 2020

2019

Boolean Minimization of Projected Sums of Products via Boolean Relations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Approximate Logic Synthesis by Symmetrization.

[BibT_eX]

[DOI]

Anna Bernasconi

Valentina Ciriani

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Rigorous Continuous Evolution of Uncertain Systems.

[BibT_eX]

[DOI]

Pieter Collins

Proceedings of the Numerical Software Verification - 12th International Workshop, 2019

Efficient Implementation of Modular Division by Input Bit Splitting.

[BibT_eX]

[DOI]

Danila A. Gorodecky

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

Complexity of Weak, Strong and Dynamic Controllability of CNCUs.

[BibT_eX]

[DOI]

Proceedings of the 1st Workshop on Artificial Intelligence and Formal Verification, 2019

Strong Controllability of Temporal Networks with Decisions.

[BibT_eX]

[DOI]

Proceedings of the 1st Workshop on Artificial Intelligence and Formal Verification, 2019

Automated Verification of Noisy Nonlinear Cyber-Physical Systems with Ariadne.

[BibT_eX]

[DOI]

Proceedings of the 1st Workshop on Artificial Intelligence and Formal Verification, 2019

2018

Formal Verification of Medical CPS: A Laser Incision Case Study.

[BibT_eX]

[DOI]

ACM Trans. Cyber Phys. Syst., 2018

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2018

Hardware realization of residue number system algorithms by Boolean functions minimization.

[BibT_eX]

[DOI]

Danila A. Gorodecky

CoRR, 2018

2017

Ongoing Work on Automated Verification of Noisy Nonlinear Systems with Ariadne.

[BibT_eX]

[DOI]

Pieter Collins

Proceedings of the Testing Software and Systems, 2017

2016

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

Using Flexibility in P-Circuits by Boolean Relations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Component-Based Design by Solving Language Equations.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

A Platform-Based Design Methodology With Contracts and Related Tools for the Design of Cyber-Physical Systems.

[BibT_eX]

[DOI]

Pierluigi Nuzzo

Proc. IEEE, 2015

Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue].

[BibT_eX]

[DOI]

Luca P. Carloni

Proc. IEEE, 2015

Formal verification of robotic surgery tasks by reachability analysis.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Games, Automata, Logics, and Formal Verification (GandALF 2013).

[BibT_eX]

[DOI]

Angelo Montanari

Gabriele Puppis

Inf. Comput., 2015

Deriving Compositionally Deadlock-Free Components over Synchronous Automata Compositions.

[BibT_eX]

[DOI]

Comput. J., 2015

Automated Synthesis of Protocol Converters with BALM-II.

[BibT_eX]

[DOI]

Proceedings of the Software Engineering and Formal Methods, 2015

Bi-Decomposition Using Boolean Relations.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

Deterministic Timed Finite State Machines: Equivalence Checking and Expressive Power.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Fifth International Symposium on Games, 2014

Verification of Robotic Surgery Tasks by Reachability Analysis: A Comparison of Tools.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

SOP restructuring by exploiting don't cares.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

Minimization of EP-SOPs via Boolean relations.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Synthesis of Implementable Control Strategies for Lazy Linear Hybrid Automata.

[BibT_eX]

[DOI]

Luigi Di Guglielmo

Sanjit A. Seshia

Proceedings of the 2013 Federated Conference on Computer Science and Information Systems, 2013

Minimization of P-circuits using Boolean relations.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Synthesis of P-circuits for logic restructuring.

[BibT_eX]

[DOI]

Integr., 2012

Ariadne: Dominance Checking of Nonlinear Hybrid Automata Using Reachability Analysis.

[BibT_eX]

[DOI]

Proceedings of the Reachability Problems - 6th International Workshop, 2012

Open Problems in Verification and Refinement of Autonomous Robotic Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Projected Don't Cares.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Computing the Evolution of Hybrid Systems using Rigorous Function Calculus.

[BibT_eX]

[DOI]

Proceedings of the 4th IFAC Conference on Analysis and Design of Hybrid Systems, 2012

2011

Robotic Surgery.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Mag., 2011

Correct-by-construction code generation from hybrid automata specification.

[BibT_eX]

[DOI]

Proceedings of the 7th International Wireless Communications and Mobile Computing Conference, 2011

An approximation algorithm for cofactoring-based synthesis.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Synthesis of Multilevel Boolean Networks.

[BibT_eX]

[DOI]

Yves Crama

Peter L. Hammer

Proceedings of the Boolean Models and Methods in Mathematics, 2010

Hardware Equivalence and Property Verification.

[BibT_eX]

[DOI]

Jie-Hong Roland Jiang

Yves Crama

Peter L. Hammer

Proceedings of the Boolean Models and Methods in Mathematics, 2010

2009

Discussion on Supervisory Control by Solving Automata Equation

[BibT_eX]

[DOI]

Victor Bushkov

Nina Yevtushenko

CoRR, 2009

Logic Minimization and Testability of 2SPP-P-Circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

The impact of EFSM composition on functional ATPG.

[BibT_eX]

[DOI]

Giuseppe Di Guglielmo

Franco Fummi

Graziano Pravadelli

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

On decomposing Boolean functions via extended cofactoring.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting.

[BibT_eX]

[DOI]

Lin Yuan

Gang Qu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Logic Minimization and Testability of 2-SPP Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Compositionally Progressive Solutions of Synchronous FSM Equations.

[BibT_eX]

[DOI]

Discret. Event Dyn. Syst., 2008

2007

FSM Encoding for BDD Representations.

[BibT_eX]

[DOI]

Wilsin Gosti

Int. J. Appl. Math. Comput. Sci., 2007

A new algorithm for the largest compositionally progressive solution of synchronous language equations.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Complexity of two-level logic minimization.

[BibT_eX]

[DOI]

Christopher Umans

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Efficient minimization of fully testable 2-SPP networks.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Idle Speed control - a Benchmark for Hybrid System Research1.

[BibT_eX]

[DOI]

Andrea Balluchi

Luca Benvenuti

Proceedings of the 2nd IFAC Conference on Analysis and Design of Hybrid Systems, 2006

2005

Efficient Solution of Language Equations Using Partitioned Representations.

[BibT_eX]

[DOI]

Alan Mishchenko

Jie-Hong Roland Jiang

Nina Yevtushenko

Proceedings of the 2005 Design, 2005

FSM re-engineering and its application in low power state encoding.

[BibT_eX]

[DOI]

Lin Yuan

Gang Qu

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Improving reachability analysis of hybrid automata for engine control.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE Conference on Decision and Control, 2004

2002

Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Optimization of Multi-Valued Multi-Level Networks.

[BibT_eX]

[DOI]

M. Gao

Jie-Hong Roland Jiang

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001

Model matching for finite-state machines.

[BibT_eX]

[DOI]

IEEE Trans. Autom. Control., 2001

Solution of Parallel Language Equations for Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

Negative thinking in branch-and-bound: the case of unate covering.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Maximal Safe Set Computation for Idle Speed Control of an Automotive Engine.

[BibT_eX]

[DOI]

Andrea Balluchi

Luca Benvenuti

Proceedings of the Hybrid Systems: Computation and Control, Third International Workshop, 2000

Hybrid controller synthesis for idle speed management of an automotive engine.

[BibT_eX]

[DOI]

Andrea Balluchi

Luca Benvenuti

Howard Wong-Toi

Proceedings of the American Control Conference, 2000

1999

Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

1998

Theory and algorithms for face hypercube embedding.

[BibT_eX]

[DOI]

Evguenii I. Goldberg

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Exact Minimization of Binary Decision Diagrams Using Implicit Techniques.

[BibT_eX]

[DOI]

Arlindo L. Oliveira

Luca P. Carloni

IEEE Trans. Computers, 1998

An Exact Input Encoding Algorithm for BDDs Representing FSMs.

[BibT_eX]

[DOI]

Wilsin Gosti

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

Symbolic two-level minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Explicit and implicit algorithms for binate covering problems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Theory and algorithms for state minimization of nondeterministic FSMs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Implicit computation of compatible sets for state minimization of ISFSMs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A fast and robust exact algorithm for face embedding.

[BibT_eX]

[DOI]

Evguenii I. Goldberg

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Negative thinking by incremental problem solving: application to unate covering.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

VIS.

[BibT_eX]

[DOI]

Gary D. Hachtel

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

VIS: A System for Verification and Synthesis.

[BibT_eX]

[DOI]

Gary D. Hachtel

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995

Implicit state minimization of non-deterministic FSMs.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

Satisfaction of input and output encoding constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

A Fully Implicit Algorithm for Exact State Minimization.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1992

Experiments on the synthesis and testability of non-scan finite state machines.

[BibT_eX]

[DOI]

Michael Pabst

A. Richard Newton

Proceedings of the conference on European design automation, 1992

1991

A Framework for Satisfying Input and Output Encoding Constraints.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

NOVA: state assignment of finite state machines for optimal two-level logic implementation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989

NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations.

[BibT_eX]

[DOI]