Tinoosh Mohsenin

Orcid: 0000-0001-5551-2124

According to our database1, Tinoosh Mohsenin authored at least 142 papers between 2003 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
TinyM<sup>2</sup>Net-V2: A Compact Low-power Software Hardware Architecture for Multimodal Deep Neural Networks.
ACM Trans. Embed. Comput. Syst., May, 2024

Reg-Tune: A Regression-Focused Fine-Tuning Approach for Profiling Low Energy Consumption and Latency.
ACM Trans. Embed. Comput. Syst., May, 2024

Energy-Aware FPGA Implementation of Spiking Neural Network with LIF Neurons.
CoRR, 2024

TinyM<sup>2</sup>Net-V3: Memory-Aware Compressed Multimodal Deep Neural Networks for Sustainable Edge Deployment.
CoRR, 2024

TinyVQA: Compact Multimodal Deep Neural Network for Visual Question Answering on Resource-Constrained Devices.
CoRR, 2024

Resource-Aware Saliency-Guided Differentiable Pruning for Deep Neural Networks.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Using LLMs for Augmenting Hierarchical Agents with Common Sense Priors.
Proceedings of the Thirty-Seventh International Florida Artificial Intelligence Research Society Conference, 2024

2023
MetaE2RL: Toward Meta-Reasoning for Energy-Efficient Multigoal Reinforcement Learning With Squeezed-Edge You Only Look Once.
IEEE Micro, 2023

Reg-TuneV2: A Hardware-Aware and Multiobjective Regression-Based Fine-Tuning Approach for Deep Neural Networks on Embedded Platforms.
IEEE Micro, 2023

Squeezed Edge YOLO: Onboard Object Detection on Edge Devices.
CoRR, 2023

LLM Augmented Hierarchical Agents.
CoRR, 2023

ReProHRL: Towards Multi-Goal Navigation in the Real World using Hierarchical Agents.
CoRR, 2023

MLAE2: Metareasoning for Latency-Aware Energy-Efficient Autonomous Nano-Drones.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Harnessing the Power of Explanations for Incremental Training: A LIME-Based Approach.
Proceedings of the 31st European Signal Processing Conference, 2023

HAC-POCD: Hardware-Aware Compressed Activity Monitoring and Fall Detector Edge POC Devices.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning.
ACM Trans. Design Autom. Electr. Syst., 2022

2022 roadmap on neuromorphic computing and engineering.
Neuromorph. Comput. Eng., 2022

Efficient Language-Guided Reinforcement Learning for Resource-Constrained Autonomous Systems.
IEEE Micro, 2022

A Hardware Accelerator for Language-Guided Reinforcement Learning.
IEEE Des. Test, 2022

Automatic Detection of Respiratory Symptoms Using a Low-Power Multi-Input CNN Processor.
IEEE Des. Test, 2022

Towards an Interpretable Hierarchical Agent Framework using Semantic Goals.
CoRR, 2022

TinyM<sup>2</sup>Net: A Flexible System Algorithm Co-designed Multimodal Learning Framework for Tiny Devices.
CoRR, 2022

A Fast Network Exploration Strategy to Profile Low Energy Consumption for Keyword Spotting.
CoRR, 2022

Neuromorphic-Enabled Security for IoT.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

E2EdgeAI: Energy-Efficient Edge Computing for Deployment of Vision-Based DNNs on Autonomous Tiny Drones.
Proceedings of the 7th IEEE/ACM Symposium on Edge Computing, 2022

An Optimization Framework for Efficient Vision-Based Autonomous Drone Navigation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Adaptive Performance Modeling of Data-intensive Workloads for Resource Provisioning in Virtualized Environment.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021

An Energy Efficient EdgeAI Autoencoder Accelerator for Reinforcement Learning.
IEEE Open J. Circuits Syst., 2021

A Flexible Multichannel EEG Artifact Identification Processor using Depthwise-Separable Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2021

Binary Precision Neural Network Manycore Accelerator.
ACM J. Emerg. Technol. Comput. Syst., 2021

Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

QS-NAS: Optimally Quantized Scaled Architecture Search to Enable Efficient On-Device Micro-AI.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Automatic Goal Generation using Dynamical Distance Learning.
CoRR, 2021

Interactive Hierarchical Guidance using Language.
CoRR, 2021

2021 Roadmap on Neuromorphic Computing and Engineering.
CoRR, 2021

Diverse Knowledge Distillation (DKD): A Solution for Improving The Robustness of Ensemble Models Against Adversarial Attacks.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Evaluation of Machine Learning-based Detection against Side-Channel Attacks on Autonomous Vehicle.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

An Energy-Efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

CoughNet: A Flexible Low Power CNN-LSTM Processor for Cough Sound Detection.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Neural Networks for Pulmonary Disease Diagnosis using Auditory and Demographic Information.
CoRR, 2020

Cluster-Based Partitioning of Convolutional Neural Networks, A Solution for Computational Energy and Complexity Reduction.
CoRR, 2020

Learning Diverse Latent Representations for Improving the Resilience to Adversarial Attacks.
CoRR, 2020

End-to-end Scalable and Low Power Multi-modal CNN for Respiratory-related Symptoms Detection.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

An Energy-Efficient Low Power LSTM Processor for Human Activity Monitoring.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Low-Power LSTM Processor for Multi-Channel Brain EEG Artifact Detection.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Compressive Sensing Based Data Acquisition Architecture for Transient Stellar Events in Crowded Star Fields.
Proceedings of the 2020 IEEE International Instrumentation and Measurement Technology Conference, 2020

Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Energy-Efficient Hardware for Language Guided Reinforcement Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Guiding Safe Reinforcement Learning Policies Using Structured Language Constraints.
Proceedings of the Workshop on Artificial Intelligence Safety, 2020

2019
SensorNet: A Scalable and Low-Power Deep Convolutional Neural Network for Multimodal Data Classification.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Big vs little core for energy-efficient Hadoop computing.
J. Parallel Distributed Comput., 2019

Heterogeneous Scheduling of Deep Neural Networks for Low-power Real-time Designs.
ACM J. Emerg. Technol. Comput. Syst., 2019

Learning from Observations Using a Single Video Demonstration and Human Feedback.
CoRR, 2019

Minimizing Classification Energy of Binarized Neural Network Inference for Wearable Devices.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

ECoST: Energy-Efficient Co-Locating and Self-Tuning MapReduce Applications.
Proceedings of the 48th International Conference on Parallel Processing, 2019

On the use of Deep Autoencoders for Efficient Embedded Reinforcement Learning.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Improving Safety in Reinforcement Learning Using Model-Based Architectures and Human Intervention.
Proceedings of the Thirty-Second International Florida Artificial Intelligence Research Society Conference, 2019

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

On the Complexity Reduction of Dense Layers from O(N2) to O(NlogN) with Cyclic Sparsely Connected Layers.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Learning Behaviors from a Single Video Demonstration Using Human Feedback.
Proceedings of the 18th International Conference on Autonomous Agents and MultiAgent Systems, 2019

XPPE: cross-platform performance estimation of hardware accelerators using machine learning.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

SENSE: Sketching Framework for Big Data Acceleration on Low Power Embedded Cores.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Accelerating Convolutional Neural Network With FFT on Embedded Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Low Overhead CS-Based Heterogeneous Framework for Big Data Acceleration.
ACM Trans. Embed. Comput. Syst., 2018

Embedded Low-Power Processor for Personalized Stress Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities.
IEEE Trans. Biomed. Circuits Syst., 2018

Energy-efficient acceleration of MapReduce applications using FPGAs.
J. Parallel Distributed Comput., 2018

Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs.
ACM J. Emerg. Technol. Comput. Syst., 2018

MPT: Multiple Parallel Tempering for High-Throughput MCMC Samplers.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

A Scalable and Low Power DCNN for Multimodal Data Classification.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Denoising Time Series Data Using Asymmetric Generative Adversarial Networks.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2018

A Real-Time Wearable FPGA-based Seizure Detection Processor Using MCMC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

SCALENet: A SCalable Low power AccELerator for Real-time Embedded Deep Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Low Power and Trusted Machine Learning.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

MC3A: Markov Chain Monte Carlo ManyCore Accelerator.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

BiNMAC: Binarized neural Network Manycore ACcelerator.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Energy Efficient Convolutional Neural Networks for EEG Artifact Detection.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Low Overhead Architectures for OMP Compressive Sensing Reconstruction Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

SPARCNet: A Hardware Accelerator for Efficient Deployment of Sparse Convolutional Networks.
ACM J. Emerg. Technol. Comput. Syst., 2017

PACENet: Energy efficient acceleration for convolutional network on embedded platform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An EEG artifact identification embedded system using ICA and multi-instance learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Accelerating convolutional neural network with FFT on tiny cores.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A Real-Time Embedded FPGA Processor for a Stand-Alone Dual-Mode Assistive Device.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Big vs little core for energy-efficient Hadoop computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

LESS: Big data sketching and Encryption on low power platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

An embedded FPGA accelerator for a stand-alone dual-mode assistive device.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Real-Time Anomaly Detection Framework for Many-Core Router through Machine-Learning Techniques.
ACM J. Emerg. Technol. Comput. Syst., 2016

Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

SVM-based real-time hardware Trojan detection for many-core platform.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Wearable seizure detection using convolutional neural networks with transfer learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Sketching-based high-performance biomedical big data processing accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A low-power multi-physiological monitoring processor for stress detection.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

Adaptive real-time Trojan detection framework through machine learning.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Low-Power Manycore Accelerator for Personalized Biomedical Applications.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Low Energy Sketching Engines on Many-Core Platform for Big Data Acceleration.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

FPGA-Based Reduction Techniques for Efficient Deep Neural Network Deployment.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

CS-Based Secured Big Data Processing on FPGA.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Application of Compressive Sensing to Gravitational Microlensing Experiments.
Proceedings of the Astroinformatics 2016, Sorrento, Italy, October 19-25, 2016, 2016

2015
Toward an Ultralow-Power Onboard Processor for Tongue Drive System.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Flexible Multichannel EEG Feature Extractor and Classifier for Seizure Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An ultra low power feature extraction and classification system for wearable seizure detection.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Utilizing deep neural nets for an embedded ECG-based biometric authentication system.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

A low power seizure detection processor based on direct use of compressively-sensed data and employing a deterministic random matrix.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Live demonstration: Towards an ultra low power on-board processor for Tongue Drive System.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Polarization-insensitive phase-transmultiplexing of CSRZ-OOK and RZ-BPSK to RZ-QPSK via XPM in a PCF.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstruction.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Comparing Raw Data and Feature Extraction for Seizure Detection with Deep Learning Methods.
Proceedings of the Twenty-Seventh International Florida Artificial Intelligence Research Society Conference, 2014

Deep Belief Networks Used on High Resolution Multichannel Electroencephalography Data for Seizure Detection.
Proceedings of the 2014 AAAI Spring Symposia, 2014

2013
LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization.
VLSI Design, 2013

A 64-core platform for biomedical signal processing.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Low-complexity FPGA implementation of compressive sensing reconstruction.
Proceedings of the International Conference on Computing, Networking and Communications, 2013

An efficient & reconfigurable FPGA and ASIC implementation of a spectral Doppler ultrasound imaging system.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
High performance compressive sensing reconstruction hardware with QRD process.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A many-core platform implemented for multi-channel seizure detection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Low power LDPC decoder with efficient stopping scheme for undecodable blocks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A reduced routing network architecture for partial parallel LDPC decoders.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders.
J. Signal Process. Syst., 2010

A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
A 167-Processor Computational Platform in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

Multi-Split-Row Threshold Decoding Implementations for LDPC Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes.
Proceedings of IEEE International Conference on Communications, 2009

2008
Architecture and Evaluation of an Asynchronous Array of Simple Processors.
J. Signal Process. Syst., 2008

AsAP: An Asynchronous Array of Simple Processors.
IEEE J. Solid State Circuits, 2008

A thresholding algorithm for improved Split-Row decoding of LDPC codes.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains.
IEEE Trans. Very Large Scale Integr. Syst., 2007

AsAP: A Fine-Grained Many-Core Platform for DSP Applications.
IEEE Micro, 2007

High-Throughput LDPC Decoders Using A Multiple Split-Row Method.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
An asynchronous array of simple processors for dsp applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Hardware and applications of AsAP: An asynchronous array of simple processors.
Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2003
VALID: Custom ASIC Verification and FPGA Education Platform.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003


  Loading...