Tinghuan Chen

Orcid: 0000-0002-9195-6619

According to our database1, Tinghuan Chen authored at least 38 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Fast Constraints Tuning via Transfer Learning and Multiobjective Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

Fast and Accurate Aging-Aware Cell Timing Model via Graph Learning.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior.
ACM Trans. Design Autom. Electr. Syst., 2024

Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization.
ACM Trans. Design Autom. Electr. Syst., 2024

Learning-driven Physically-aware Large-scale Circuit Gate Sizing.
CoRR, 2024

An analysis of TinyML@ICCAD for implementing AI on low-power microprocessor.
Sci. China Inf. Sci., 2024

Efficient Subgraph Matching Framework for Fast Subcircuit Identification.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

IncreMacro: Incremental Macro Placement Refinement.
Proceedings of the 2024 International Symposium on Physical Design, 2024

A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

CBTune: Contextual Bandit Tuning for Logic Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Aging-Aware Critical Path Selection via Graph Attention Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Machine Learning in Advanced IC Design: A Methodological Survey.
IEEE Des. Test, February, 2023

PTPT: Physical Design Tool Parameter Tuning via Multi-Objective Bayesian Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Fast and Accurate Wire Timing Estimation Based on Graph Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Mixed-Type Wafer Failure Pattern Recognition.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design.
ACM Trans. Design Autom. Electr. Syst., 2022

An Efficient Sharing Grouped Convolution via Bayesian Learning.
IEEE Trans. Neural Networks Learn. Syst., 2022

Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A fast parameter tuning framework via transfer learning and multi-objective bayesian optimization.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey (Invited Paper).
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Leveraging Spatial Correlation for Sensor Drift Calibration in Smart Building.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Fast and Efficient DNN Deployment via Deep Gaussian Transfer Learning.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Machine Learning in Nanometer AMS Design-for-Reliability : (Invited Paper).
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2019
Recent advances in convolutional neural network acceleration.
Neurocomputing, 2019

Power-Driven DNN Dataflow Optimization on FPGA.
Proceedings of the International Conference on Computer-Aided Design, 2019

Sensor Drift Calibration via Spatial Correlation Model in Smart Building.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Electricity Theft Detection Using Generative Models.
Proceedings of the IEEE 30th International Conference on Tools with Artificial Intelligence, 2018

2017
Blind Equalization of Constant Modulus Signals Based on Gaussian Process for Classification.
Wirel. Pers. Commun., 2017

2016
Image Arbitrary-Ratio Down- and Up-Sampling Scheme Exploiting DCT Low Frequency Components and Sparsity in High Frequency Components.
IEICE Trans. Inf. Syst., 2016


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