Ting-Sheng Chen

Orcid: 0000-0003-0456-9790

According to our database1, Ting-Sheng Chen authored at least 12 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Real-Time Multi-User Detection Engine Design for IoT Applications via Modified Sparsity Adaptive Matching Pursuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Hybrid LAE-CMOS Force-Sensing System Employing TFT-Based Compressed Sensing for Scalability of Tactile Sensing Skins.
IEEE Trans. Biomed. Circuits Syst., 2019

A 232-1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring.
IEEE J. Solid State Circuits, 2019

Hybrid System for Efficient LAE-CMOS Interfacing in Large-Scale Tactile-Sensing Skins via TFT-Based Compressed Sensing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

More Effective Power Network Prototyping by Analytical and Centroid Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing.
IEEE/ACM Trans. Netw., 2018

A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoring.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2010
CAD reference flow for 3D via-last integrated circuits.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010


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