Ting An

According to our database1, Ting An authored at least 16 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Nondestructive Testing and Visualization of Catechin Content in Black Tea Fermentation Using Hyperspectral Imaging.
Sensors, 2021

2020
Embryonics Based Phased Array Antenna Structure With Self-Repair Ability.
IEEE Access, 2020

2019
Feasibility and Reliability Analysis of LCC DC Grids and LCC/VSC Hybrid DC Grids.
IEEE Access, 2019

2017
Application of Genetic Algorithm Based on F-Ratio Rule in Signal Feature Selection.
Proceedings of the 10th International Symposium on Computational Intelligence and Design, 2017

2015
Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method.
Microelectron. Reliab., 2015

2014
Architectures of self-controllable digital operators. (Architectures d'opérateurs numérique auto-contrôlables).
PhD thesis, 2014

Efficient implementation for accurate analysis of CED circuits against multiple faults.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Analytical method for reliability assessment of concurrent checking circuits under multiple faults.
Proceedings of the 37th International Convention on Information and Communication Technology, 2014

Simulation study of aging in CMOS binary adders.
Proceedings of the 37th International Convention on Information and Communication Technology, 2014

2013
Evaluation of fault-tolerant composite field AES S-boxes under multiple transient faults.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Modeling of transient faults and fault-tolerant design in nanoelectronics.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology.
Proceedings of Eurocon 2013, 2013

Reliability analysis of combinational circuits with the influences of noise and single-event transients.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

A low cost reliable architecture for S-Boxes in AES processors.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Parallel scaling-free and area-time efficient CORDIC algorithm.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Transient fault analysis of CORDIC processor.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012


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