Timothy M. Hollis

Orcid: 0000-0002-4579-206X

According to our database1, Timothy M. Hollis authored at least 6 papers between 2005 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling.
IEEE J. Solid State Circuits, 2022

2021

2009
Data Bus Inversion in High-Speed Memory Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008
Jittery Signal Generation for High-Speed Interconnect Simulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2006
Mitigating ISI Through Self-Calibrating Continuous-Time Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2005
Optimization of MOS amplifier performance through channel length and inversion level selection.
IEEE Trans. Circuits Syst. II Express Briefs, 2005


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