Tim Kogel
Orcid: 0000-0002-7397-2615
According to our database1,
Tim Kogel
authored at least 28 papers
between 2001 and 2022.
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Bibliography
2022
Int. J. Parallel Program., 2022
2020
An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
2017
Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis.
Proceedings of the Handbook of Hardware/Software Codesign., 2017
2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
2009
Proceedings of the 46th Design Automation Conference, 2009
2008
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.
Int. J. Embed. Syst., 2008
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.
Int. J. Embed. Syst., 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Integrated system-level modeling of network-on-chip enabled multi-processor platforms.
Kluwer, ISBN: 978-1-4020-4825-8, 2006
2005
OCP TLM for Architectural Modelling.
Proceedings of the Forum on specification and Design Languages, 2005
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.
Proceedings of the 2005 Design, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the Computer Systems: Architectures, 2004
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.
Proceedings of the Computer Systems: Architectures, 2004
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Proceedings of the 2003 International Symposium on System-on-Chip, 2003
A modular simulation framework for architectural exploration of on-chip interconnection networks.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
2001
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001