Tim Fritzmann

Orcid: 0000-0002-5483-4292

According to our database1, Tim Fritzmann authored at least 17 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography.
J. Cryptogr. Eng., April, 2024

Post-Quantum Signatures on RISC-V with Hardware Acceleration.
ACM Trans. Embed. Comput. Syst., March, 2024

2022
Towards Secure Coprocessors and Instruction Set Extensions for Acceleration of Post-Quantum Cryptography.
PhD thesis, 2022

Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Hardware Accelerated FrodoKEM on RISC-V.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021
Post-quantum cryptography for automotive systems.
Microprocess. Microsystems, November, 2021

2020
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Strengthening Post-Quantum Security for Automotive Systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
The Influence of LWE/RLWE Parameters on the Stochastic Dependence of Decryption Failures.
IACR Cryptol. ePrint Arch., 2019

Efficient and Flexible Low-Power NTT for Lattice-Based Cryptography.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Analysis of Error-Correcting Codes for Lattice-Based Key Exchange.
IACR Cryptol. ePrint Arch., 2018

Efficient Hardware/Software Co-design for NTRU.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

Secure and Compact Full NTRU Hardware Implementation.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Error-Correcting Codes for Lattice-Based Key Exchange.
Proceedings of the 28. Krypto-Tag, 2018


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