Tianzhu Xiong

According to our database, Tianzhu Xiong authored at least 18 papers between 2020 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation.

Tianzhu Xiong, Yuyang Ye, Xin Si, Jun Yang

IEEE Trans. Very Large Scale Integr. Syst., January, 2025

2024

A 22-nm 264-GOPS/mm² 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs.

Feiran Liu, Anran Yin, Chen Xue, Bo Wang, Zhongyuan Feng, Han Liu, Xiang Li, Hui Gao, Tianzhu Xiong, Xin Si

IEEE Trans. Very Large Scale Integr. Syst., December, 2024

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture.

Xi Chen, Yitong Zhao, An Guo, Jinwu Chen, Fangyuan Dong, Zhaoyang Zhang, Tianzhu Xiong, Bo Wang, Yuyao Kong, Xin Si

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

An INT8 Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly Shift-Feed Register Design.

Jinwu Chen, Yitong Zhao, Tianzhu Xiong, Xin Si

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices.

Yongliang Zhou, Yiming Wei, Tianzhu Xiong, Zixuan Zhou, Zhen Yang, Xiao Lin, Wei Hu, Xiulong Wu, Chunyu Peng

Microelectron. J., 2024

CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency.

Chenchen Deng, Tianzhu Xiong, Zhaoshi Li, Zhiwei Liu, Yao Wang, Jianfeng Zhu, Jun Yang, Shaojun Wei, Leibo Liu

Sci. China Inf. Sci., 2024

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.

An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.

Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.

Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang

Sci. China Inf. Sci., October, 2023

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.

Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.

An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A Charge-Digital Hybrid Compute-In-Memory Macro with full precision 8-bit Multiply-Accumulation for Edge Computing Devices.

Jinwu Chen, Tianzhu Xiong, Xin Si

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.

Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations.

An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators.

Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices.

Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si

Proceedings of the International Conference on UK-China Emerging Technologies, 2021

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices.

Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang

Proceedings of the 18th International SoC Design Conference, 2021

2020

CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture.

Dibei Chen, Zhaoshi Li, Tianzhu Xiong, Zhiwei Liu, Jun Yang, Shouyi Yin, Shaojun Wei, Leibo Liu

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020