Tianyi Lu
Orcid: 0009-0003-7803-194X
According to our database1,
Tianyi Lu
authored at least 30 papers
between 2016 and 2024.
Collaborative distances:
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Bibliography
2024
KSL-POSE: A Real-Time 2D Human Pose Estimation Method Based on Modified YOLOv8-Pose Framework.
Sensors, October, 2024
A Feature Selection Method Based on Feature-Label Correlation Information and Self-Adaptive MOPSO.
Neural Process. Lett., April, 2024
Performance Assessment of a High-Frequency Radar Network for Detecting Surface Currents in the Pearl River Estuary.
Remote. Sens., January, 2024
Variational Characterization and Rayleigh Quotient Iteration of 2D Eigenvalue Problem with Applications.
SIAM J. Matrix Anal. Appl., 2024
CoRR, 2024
Population dynamics modeling of crowdsourcing as an evolutionary Cooperation-Competition game for fulfillment capacity balancing and optimization of smart manufacturing services.
Comput. Ind. Eng., 2024
Proceedings of the 32nd ACM International Conference on Multimedia, MM 2024, Melbourne, VIC, Australia, 28 October 2024, 2024
Proceedings of the Thirty-Third International Joint Conference on Artificial Intelligence, 2024
Proceedings of the Computer Vision - ECCV 2024, 2024
2023
VideoAssembler: Identity-Consistent Video Generation with Reference Entities using Diffusion Model.
CoRR, 2023
CoRR, 2023
2D Eigenvalue Problem III: Convergence Analysis of the 2D Rayleigh Quotient Iteration.
CoRR, 2023
2022
Numer. Linear Algebra Appl., 2022
Research on steelmaking-continuous casting production scheduling problem with uncertain processing time based on Lagrangian relaxation framework.
Int. J. Autom. Control., 2022
2021
Proceedings of the 16th International Conference on Computer Science & Education, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
2019
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width.
IEEE J. Solid State Circuits, 2019
2018
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.
IEEE J. Solid State Circuits, 2018
IEEE Access, 2018
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Operating Data-driven Predictive Analytics for Tele-diagnosis of Refrigeration Systems: A Case Study.
Proceedings of the 2018 IEEE International Conference on Industrial Engineering and Engineering Management, 2018
2017
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory.
IEEE Trans. Parallel Distributed Syst., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
2016
Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016