Tianxiang Shao

According to our database, Tianxiang Shao authored at least 6 papers between 2019 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages.

Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang

IEEE Trans. Very Large Scale Integr. Syst., 2021

2020

TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages.

Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi

IEEE Trans. Very Large Scale Integr. Syst., 2020

Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM.

Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang, Longxing Shi

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

TYMER: A Yield-based Performance Model for Timing-speculation SRAM.

Shan Shen, Liang Pang, Tianxiang Shao, Ming Ling, Xiao Shi, Longxing Shi

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.

Ming Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, Jun Yang

IEEE Access, 2019

RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.

Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang

Proceedings of the International Symposium on Memory Systems, 2019