We stand with Ukraine

We stand with Ukraine

Tiantian Liu

Affiliations:

Chinese Academy of Sciences, Cloud Computing Center, Dongguan, China
City University of Hong Kong, Department of Computer Science, Kowloon, Hong Kong (PhD 2012)

According to our database¹, Tiantian Liu authored at least 17 papers between 2008 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

Online presence:

on ieeexplore.ieee.org

On csauthors.net:

Bibliography

2022

Deep Reinforcement-Learning-Guided Backup for Energy Harvesting Powered Systems.

[BibT_eX]

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2017

State Asymmetry Driven State Remapping in Phase Change Memory.

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2013

Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory.

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IEEE Trans. Signal Process., 2013

Joint variable partitioning and bank selection instruction optimization for partitioned memory architectures.

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ACM Trans. Embed. Comput. Syst., 2013

Register allocation for embedded systems to simultaneously reduce energy and temperature on registers.

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ACM Trans. Embed. Comput. Syst., 2013

2012

Instruction Cache Locking for Embedded Systems using Probability Profile.

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J. Signal Process. Syst., 2012

Instruction cache locking for multi-task real-time embedded systems.

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Real Time Syst., 2012

Register allocation for write activity minimization on non-volatile main memory for embedded systems.

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J. Syst. Archit., 2012

Analysis and approximation for bank selection instruction minimization on partitioned memory architecture.

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J. Comb. Optim., 2012

2011

Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC.

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J. Parallel Distributed Comput., 2011

Register allocation for simultaneous reduction of energy and peak temperature on registers.

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Proceedings of the Design, Automation and Test in Europe, 2011

Register allocation for write activity minimization on non-volatile main memory.

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Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC.

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Proceedings of the 39th International Conference on Parallel Processing, 2010

Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks.

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Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks.

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Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking.

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Proceedings of the 15th IEEE Real-Time and Embedded Technology and Applications Symposium, 2009

2008

Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.

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Edwin Hsing-Mean Sha

Proceedings of the IEEE International Conference on Acoustics, 2008

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