Tiantao Lu

Orcid: 0000-0003-4431-811X

According to our database1, Tiantao Lu authored at least 12 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2017
Low-Power Clock Tree Synthesis for 3D-ICs.
ACM Trans. Design Autom. Electr. Syst., 2017

TSV-Based 3-D ICs: Design Methods and Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Security and Vulnerability Implications of 3D ICs.
IEEE Trans. Multi Scale Comput. Syst., 2016

Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Electromigration-aware placement for 3D-ICs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015
Modeling and Layout Optimization for Tapered TSVs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Gated low-power clock tree synthesis for 3D-ICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2013
Detailed electrical and reliability study of tapered TSVs.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013


  Loading...