Tian-Chun Ye
Orcid: 0000-0002-2384-9037Affiliations:
- Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China
According to our database1,
Tian-Chun Ye
authored at least 38 papers
between 2005 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology.
Microelectron. J., 2024
2023
Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme.
IEICE Electron. Express, 2023
The Effects of $\gamma$ Radiation-Induced Trapped Charges on Single Event Transient in DSOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
A Two-Layer Ensemble Method for Detecting Epileptic Seizures Using a Self-Annotation Bracelet With Motor Sensors.
IEEE Trans. Instrum. Meas., 2022
Flexible Hotspot Detection Based on Fully Convolutional Network With Transfer Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Comput. Methods Programs Biomed., 2022
The Synergetic Effects of Total Ionizing Dose and High Temperature on 180 nm DSOI Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Design and VLSI Implementation of a Sorted MMSE QR Decomposition for 4×4 MIMO Detectors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
IEICE Electron. Express, 2021
Proceedings of the 10th International IEEE/EMBS Conference on Neural Engineering, 2021
2020
A Low-Spur and Intrinsically Aligned IL-PLL With Self-Feedback Injection Locked RO and Pseudo-Random Injection Locked Technique.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
A Low Phase Noise, High Phase Accuracy Quadrature LC-VCO With Dual-Tail Current Biasing to Insert Reconfigurable Phase Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers.
IEICE Electron. Express, 2020
Influence of an ALD TiN capping layer on the PBTI characteristics of n-FinFET with ALD HfO<sub>2</sub>/TiN-capping/TiAl gate stacks.
Sci. China Inf. Sci., 2020
2019
IEICE Electron. Express, 2019
IEEE Commun. Lett., 2019
2018
FPGA and ASIC implementation of reliable and effective architecture for a LTE downlink transmitter.
IEICE Electron. Express, 2018
IEICE Electron. Express, 2018
IEEE Commun. Lett., 2018
2017
A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEEE Commun. Lett., 2017
2016
Accurate lifetime prediction for channel hot carrier stress on sub-1 nm equivalent oxide thickness HK/MG nMOSFET with thin titanium nitride capping layer.
Microelectron. Reliab., 2016
2015
Microelectron. J., 2015
2014
A 95 dB dynamic range automatic gain control circuits and systems for Multi-standard Digital TV tuner.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
IEICE Electron. Express, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2011
Sci. China Inf. Sci., 2011
2009
A simple prediction method for composite rectangular microcantilevers with equal width and the dimensional optimization.
Microelectron. J., 2009
Proceedings of the 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2009
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005