Tiago Reimann
Orcid: 0000-0002-3730-0213
According to our database1,
Tiago Reimann
authored at least 11 papers
between 2009 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2016
Challenges of cell selection algorithms in industrial high performance microprocessor designs.
Integr., 2016
Proceedings of the 2016 on International Symposium on Physical Design, 2016
2015
Gate sizing and threshold voltage assignment for high performance microprocessor designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms.
Proceedings of the 28th International Conference on Computer Design, 2010
2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009