Thorsten Jungeblut
Orcid: 0000-0001-7425-8766Affiliations:
- Bielefeld University, CITEC, Germany
- University of Paderborn, Heinz Nixdorf Institute, Germany
According to our database1,
Thorsten Jungeblut
authored at least 40 papers
between 2009 and 2025.
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Bibliography
2025
RAVSim v2.0: Enhanced visualization and comparative analysis for neural network models.
SoftwareX, 2025
2024
A Hybrid Spiking-Convolutional Neural Network Approach for Advancing Machine Learning Models.
CoRR, 2024
Design-Space Exploration of SNN Models using Application-Specific Multi-Core Architectures.
CoRR, 2024
Encryption Techniques for Privacy-Preserving CNN Models: Performance and Practicality in Urban AI Applications.
Proceedings of the 2nd ACM SIGSPATIAL International Workshop on Advances in Urban-AI, 2024
Proceedings of the Companion Proceedings of the 8th International Conference on the Art, 2024
Poster: Selection of Optimal Neural Model using Spiking Neural Network for Edge Computing<sup>*</sup>.
Proceedings of the 44th IEEE International Conference on Distributed Computing Systems, 2024
A Spike Vision Approach for Multi-object Detection and Generating Dataset Using Multi-core Architecture on Edge Device.
Proceedings of the Engineering Applications of Neural Networks, 2024
2023
Evaluation of Spiking Neural Nets-Based Image Classification Using the Runtime Simulator RAVSim.
Int. J. Neural Syst., September, 2023
Exploring spiking neural networks: a comprehensive analysis of mathematical models and applications.
Frontiers Comput. Neurosci., February, 2023
Proceedings of the Advances in Computational Intelligence, 2023
Streamlined Training of GCN for Node Classification with Automatic Loss Function and Optimizer Selection.
Proceedings of the Engineering Applications of Neural Networks, 2023
2022
A Framework for Learning Event Sequences and Explaining Detected Anomalies in a Smart Home Environment.
Künstliche Intell., 2022
Proceedings of the Engineering Applications of Neural Networks, 2022
2019
Proceedings of the 2019 IEEE International Conference on Systems, Man and Cybernetics, 2019
2018
CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories.
IEEE Trans. Parallel Distributed Syst., 2018
Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems.
CoRR, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Scalable Mapping of Streaming Applications onto MPSoCs Using Optimistic Mixed Integer Linear Programming.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017
Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 14th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2017
2016
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016
Evidenzkarten-basierte Sensorfusion zur Umfelderkennung und Interpretation in der Ernte.
Proceedings of the Informatik in der Land-, Forst- und Ernährungswirtschaft, Fokus: Intelligente Systeme, 2016
2015
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015
Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Universelle Echtzeit-Ethernet Architektur zur Integration in rekonfigurierbare Automatisierungssysteme.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
A communication model and partitioning algorithm for streaming applications for an embedded MPSoC.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014
2013
A systematic approach for optimized bypass configurations for application-specific embedded processors.
ACM Trans. Embed. Comput. Syst., 2013
A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control.
IEEE J. Solid State Circuits, 2013
Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
2010
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010
Proceedings of the Mobile Lightweight Wireless Systems, 2010
2009
Proceedings of the Analysis, 2009