Thomas Polzer

J. Circuits Syst. Comput., 2019

2018

Refined metastability characterization using a time-to-digital converter.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017

A Model for the Metastability Delay of Sequential Elements.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2017

Measuring metastability using a time-to-digital converter.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Measuring Metastability with Free-Running Clocks.

[BibT_eX]

[DOI]

Robert Najvirt

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Metastability-Aware Memory-Efficient Time-to-Digital Converters.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016

On the Appropriate Handling of Metastable Voltages in FPGAs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

A general approach for comparing metastable behavior of digital CMOS gates.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

Enhanced Metastability Characterization Based on AC Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Measuring the Distribution of Metastable Upsets over Time.

[BibT_eX]

[DOI]

Varadan Savulimedu Veeravalli

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Containment of Metastable Voltages in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2013

An infrastructure for accurate characterization of single-event transients in digital circuits.

[BibT_eX]

[DOI]

Kerstin Schneider-Hornstein

Microprocess. Microsystems, 2013

Metastability characterization for muller C-elements.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

SET propagation in micropipelines.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Digital Late-Transition Metastability Simulation Model.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

An Approach for Efficient Metastability Characterization of FPGAs through the Designer.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012

Muller C-Element Metastability Containment.

[BibT_eX]

[DOI]

Varadan Savulimedu Veeravalli

Jakob Lechner

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip.

[BibT_eX]

[DOI]

Ulrich Schmid

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding.

[BibT_eX]

[DOI]

Jakob Lechner

Martin Lampacher

Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2009

A Metastability-Free Multi-synchronous Communication Scheme for SoCs.

[BibT_eX]

[DOI]

Thomas Handl