Thomas P. Warwick

According to our database, Thomas P. Warwick authored at least 5 papers between 1999 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC Applications.

Thomas P. Warwick, Gustavo Rivera, David Waite, James Russell, Jeffrey Smith

Proceedings of the 2008 IEEE International Test Conference, 2008

2003

Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements.

Thomas P. Warwick

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region.

Thomas P. Warwick

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999

An accurate simulation model of the ATE test environment for very high speed devices.

Thomas P. Warwick, Jung Cho, Yi Cai, Bill Ortner

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

High speed digital transceivers: A challenge for manufacturing.

Clifford B. Cole, Thomas P. Warwick

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999