Thomas P. Bushey

According to our database, Thomas P. Bushey authored at least 2 papers in 1989.

Collaborative distances:

• Dijkstra number of seven.
• Erdős number of six.

1989

An improved high-performance logic gate using series diode and resistor loads for ECL/CML applications.

Bor-Yuan Hwang, Thomas P. Bushey

IEEE J. Solid State Circuits, August, 1989

A bipolar ECL static RAM using polysilicon-diode loaded memory cell.

Bor-Yuan Hwang, Thomas P. Bushey, James A. Kirchgessner, Samuel A. Foertsch, James J. Stipanuk, Larry Marshbanks, Juan A. Hernandez, Eric R. Herald

IEEE J. Solid State Circuits, April, 1989