Thomas M. Conte

According to our database, Thomas M. Conte authored at least 119 papers between 1984 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Qwerty: A Basis-Oriented Quantum Programming Language.

Austin Adams, Sharjeel Khan, Jeffrey S. Young, Thomas M. Conte

CoRR, 2024

5 Year Update to the Next Steps in Quantum Computing.

Kenneth Brown, Fred Chong, Kaitlin N. Smith, Tom Conte, Austin Adams, Aniket S. Dalvi, Christopher Kang, Joshua Viszlai

CoRR, 2024

2023

Status Update on the IEEE Rebooting Computing Initiative.

Thomas M. Conte

Proceedings of the IEEE John Vincent Atanasoff International Symposium on Modern Computing, 2023

The Invention of Electronic Digital Computing - Plenary Panel Summary.

John Vincent Atanasoff, Gordon Bell, Kiril L. Boyanov, Charles G. Call, Carl K. Chang, Thomas M. Conte, Vladimir Getov, John L. Gustafson, Hironori Kasahara, Dejan S. Milojicic, Michael R. Williams

Proceedings of the IEEE John Vincent Atanasoff International Symposium on Modern Computing, 2023

Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models.

Akihiro Hayashi, Austin Adams, Jeffrey Young, Alexander J. McCaskey, Eugene F. Dumitrescu, Vivek Sarkar, Thomas M. Conte

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

2022

Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems.

Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook

IEEE Trans. Computers, 2022

"Smarter" NICs for faster molecular dynamics: a case study.

Sara Karamati, Clayton Hughes, K. Scott Hemmert, Ryan E. Grant, Whit Schonbein, Scott Levy, Thomas M. Conte, Jeffrey Young, Richard W. Vuduc

Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

2021

SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads.

Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook

ACM Trans. Archit. Code Optim., 2021

Advancing Computing's Foundation of US Industry & Society.

Thomas M. Conte, Ian T. Foster, William Gropp, Mark D. Hill

CoRR, 2021

A vision to compute like nature: thermodynamically.

Todd Hylton, Thomas M. Conte, Mark D. Hill

Commun. ACM, 2021

Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed.

Austin Adams, Elton Pinto, Jeffrey Young, Creston D. Herold, Alexander J. McCaskey, Eugene F. Dumitrescu, Thomas M. Conte

Proceedings of the 2021 International Conference on Rebooting Computing (ICRC), Los Alamitos, CA, USA, November 30, 2021

2020

Programming Strategies for Irregular Algorithms on the Emu Chick.

Eric R. Hein, Srinivas Eswar, Abdurrahman Yasar, Jiajia Li, Jeffrey S. Young, Thomas M. Conte, Ümit V. Çatalyürek, Richard W. Vuduc, E. Jason Riedy, Bora Uçar

ACM Trans. Parallel Comput., 2020

MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams.

Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook

ACM Trans. Archit. Code Optim., 2020

Evolving Methods for Evaluating and Disseminating Computing Research.

Benjamin Zorn, Tom Conte, Keith Marzullo, Suresh Venkatasubramanian

CoRR, 2020

Intrepydd: performance, productivity, and portability for data science application kernels.

Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar

Proceedings of the 2020 ACM SIGPLAN International Symposium on New Ideas, 2020

Special Session: Exploring the Ultimate Limits of Adiabatic Circuits.

Michael P. Frank, Robert W. Brocato, Thomas M. Conte, Alexander H. Hsia, Anirudh Jain, Nancy A. Missert, Karpur Shukla, Brian D. Tierney

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

A microbenchmark characterization of the Emu chick.

Jeffrey S. Young, Eric R. Hein, Srinivas Eswar, Patrick Lavin, Jiajia Li, E. Jason Riedy, Richard W. Vuduc, Tom Conte

Parallel Comput., 2019

Thermodynamic Computing.

Tom Conte, Erik DeBenedictis, Natesh Ganesh, Todd Hylton, John Paul Strachan, R. Stanley Williams, Alexander A. Alemi, Lee Altenberg, Gavin E. Crooks, James P. Crutchfield, Lídia del Rio, Josh Deutsch, Michael Robert DeWeese, Khari Douglas, Massimiliano Esposito, Michael P. Frank, Robert Fry, Peter Harsha, Mark D. Hill, Christopher T. Kello, Jeff Krichmar, Suhas Kumar, Shih-Chii Liu, Seth Lloyd, Matteo Marsili, Ilya Nemenman, Alex Nugent, Norman H. Packard, Dana Randall, Peter Sadowski, Narayana Santhanam, Robert Shaw, Adam Z. Stieg, Elan Stopnitzky, Christof Teuscher, Chris Watkins, David H. Wolpert, J. Joshua Yang, Yan Yufik

CoRR, 2019

Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures.

Will Powell, E. Jason Riedy, Jeffrey S. Young, Thomas M. Conte

Proceedings of the Practice and Experience in Advanced Research Computing on Rise of the Machines (learning), 2019

Application Performance of Physical System Simulations.

Vladimir Getov, Peter M. Kogge, Thomas M. Conte

Proceedings of the Parallel Computing: Technology Trends, 2019

Experimental Insights from the Rogues Gallery.

Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth

Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019

2018

Extending Moore's Law via Computationally Error-Tolerant Computing.

Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank

ACM Trans. Archit. Code Optim., 2018

Iterative Modulo Scheduling.

Onur Mutlu, Scott A. Mahlke, Thomas M. Conte, Wen-Mei W. Hwu

IEEE Micro, 2018

Standards: Roadmapping Computer Technology Trends Enlightens Industry.

F. D. Wright, Thomas M. Conte

Computer, 2018

Rebooting Computers to Avoid Meltdown and Spectre.

Thomas M. Conte, Erik P. DeBenedictis, Avi Mendelson, Dejan S. Milojicic

Computer, 2018

Tackling memory access latency through DRAM row management.

Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang

Proceedings of the International Symposium on Memory Systems, 2018

An Initial Characterization of the Emu Chick.

Eric R. Hein, Tom Conte, Jeffrey Young, Srinivas Eswar, Jiajia Li, Patrick Lavin, Richard W. Vuduc, E. Jason Riedy

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures.

Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

Architectures for the Post-Moore Era.

Jeffrey S. Vetter, Erik P. DeBenedictis, Thomas M. Conte

IEEE Micro, 2017

Challenges to Keeping the Computer Industry Centered in the US.

Thomas M. Conte, Erik P. DeBenedictis, R. Stanley Williams, Mark D. Hill

CoRR, 2017

Sustaining Moore's Law with 3D Chips.

Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte, Paolo A. Gargini

Computer, 2017

Rebooting Computing: The Road Ahead.

Thomas M. Conte, Erik P. DeBenedictis, Paolo A. Gargini, Elie K. Track

Computer, 2017

The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing.

Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C.

Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016

A Brief Survey of Non-Residue Based Computational Error Correction.

Sriseshan Srikanth, Bobin Deng, Thomas M. Conte

CoRR, 2016

Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging.

Rishiraj A. Bheda, Thomas M. Conte, Jeffrey S. Vetter

Proceedings of the Second International Symposium on Memory Systems, 2016

Computationally-redundant energy-efficient processing for y'all (CREEPY).

Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Energy efficiency limits of logic and memory.

Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

2015

Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs.

Brian P. Railing, Eric R. Hein, Thomas M. Conte

ACM Trans. Archit. Code Optim., 2015

Rebooting Computing: New Strategies for Technology Scaling.

Thomas M. Conte, Elie K. Track, Erik DeBenedictis

Computer, 2015

The Computer Society Must Change.

Thomas M. Conte

Computer, 2015

A Time of Change.

Tom Conte

Computer, 2015

Rebooting Computing and Low-Power Image Recognition Challenge.

Yung-Hsiang Lu, Alan M. Kadin, Alexander C. Berg, Thomas M. Conte, Erik P. DeBenedictis, Rachit Garg, Ganesh Gingade, Bichlien Hoang, Yongzhen Huang, Boxun Li, Jingyu Liu, Wei Liu, Huizi Mao, Junran Peng, Tianqi Tang, Elie K. Track, Jingqiu Wang, Tao Wang, Yu Wang, Jun Yao

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Manifold: A parallel simulation framework for multicore systems.

Jun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili

Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

2013

High-speed formal verification of heterogeneous coherence hierarchies.

Jesse G. Beu, Jason A. Poovey, Eric R. Hein, Thomas M. Conte

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems.

Jun Wang, Jesse G. Beu, Sudhakar Yalamanchili, Tom Conte

Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Accelerating Multi-threaded Application Simulation through Barrier-Interval Time-Parallelism.

Paul D. Bryan, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte

Proceedings of the 20th IEEE International Symposium on Modeling, 2012

Extrapolation Pitfalls When Evaluating Limited Endurance Memory.

Rishiraj A. Bheda, Jesse G. Beu, Brian P. Railing, Thomas M. Conte

Proceedings of the 20th IEEE International Symposium on Modeling, 2012

2011

Manager-client pairing: a framework for implementing coherence hierarchies.

Jesse G. Beu, Michel C. Rosier, Thomas M. Conte

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Parallel Pattern Detection for Architectural Improvements.

Jason A. Poovey, Brian P. Railing, Thomas M. Conte

Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

Energy efficient Phase Change Memory based main memory for future high performance systems.

Rishiraj A. Bheda, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

2009

A Benchmark Characterization of the EEMBC Benchmark Suite.

Jason A. Poovey, Thomas M. Conte, Markus Levy, Shay Gal-On

IEEE Micro, 2009

Embedded Multicore Processors and Systems.

Markus Levy, Thomas M. Conte

IEEE Micro, 2009

On power and energy trends of IEEE 802.11n PHY.

Balaji V. Iyer, Thomas M. Conte

Proceedings of the 12th International Symposium on Modeling Analysis and Simulation of Wireless and Mobile Systems, 2009

2008

A Power Model for Register-Sharing Structures.

Balaji V. Iyer, Thomas M. Conte

Proceedings of the Distributed Embedded Systems: Design, 2008

Energy-aware opcode design.

Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte

Proceedings of the 26th International Conference on Computer Design, 2008

2007

Reverse State Reconstruction for Sampled Microarchitectural Simulation.

Paul D. Bryan, Michel C. Rosier, Thomas M. Conte

Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Combining cluster sampling with single pass methods for efficient sampling regimen design.

Paul D. Bryan, Thomas M. Conte

Proceedings of the 25th International Conference on Computer Design, 2007

Keynote: Insight, Not (Random) Numbers: An Embedded Perspective.

Thomas M. Conte

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

2005

High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm.

Emre Özer, Thomas M. Conte

IEEE Trans. Parallel Distributed Syst., 2005

Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction.

Huiyang Zhou, Thomas M. Conte

IEEE Trans. Computers, 2005

Spectral prefetcher: An effective mechanism for L2 cache prefetching.

Saurabh Sharma, Jesse G. Beu, Thomas M. Conte

ACM Trans. Archit. Code Optim., 2005

Configurable string matching hardware for speeding up intrusion detection.

Monther Aldwairi, Thomas M. Conte, Paul D. Franzon

SIGARCH Comput. Archit. News, 2005

Insight, not (random) numbers.

Thomas M. Conte

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

2004

Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems.

Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete

IEEE Micro, 2004

2003

Adaptive mode control: A static-power-efficient cache design.

Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte

ACM Trans. Embed. Comput. Syst., 2003

Modeling Value Speculation: An Optimal Edge Selection Problem.

Chao-ying Fu, Jill T. Bodine, Thomas M. Conte

IEEE Trans. Computers, 2003

Detecting Global Stride Locality in Value Streams.

Huiyang Zhou, Jill Flanagan, Thomas M. Conte

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002

Choosing the Brain(s) of an Embedded System.

Thomas M. Conte

Computer, 2002

Code Size Efficiency in Global Scheduling for ILP Processors.

Huiyang Zhou, Thomas M. Conte

Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2001

Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors.

Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte

Proceedings of the Languages and Compilers for Parallel Computing, 2001

Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors.

Emre Özer, Thomas M. Conte, Saurabh Sharma

Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001

2000

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design.

Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen

IEEE Trans. Very Large Scale Integr. Syst., 2000

Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility.

Thomas M. Conte, Sumedh W. Sathaye

IEEE Trans. Computers, 2000

A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization.

Kim M. Hazelwood, Thomas M. Conte

Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999

Challenges in processor modeling and validation [Guest Editors?? introduction].

Pradip Bose, Thomas M. Conte, Todd M. Austin

IEEE Micro, 1999

Editors' Introduction.

Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman

Int. J. Parallel Program., 1999

Editor's Introduction.

Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman

Int. J. Parallel Program., 1999

Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors.

Sergei Y. Larin, Thomas M. Conte

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Dynamically Programmable Cache Evaluation and Virtualization.

Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998

Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation.

Thomas M. Conte, Mary Ann Hirsch, Wen-mei W. Hwu

IEEE Trans. Computers, 1998

MPS: Miss-Path Scheduling for Multiple-Issue Processors.

Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte

IEEE Trans. Computers, 1998

Subword extensions for video processing on mobile systems.

Matthew D. Jennings, Thomas M. Conte

IEEE Concurr., 1998

Performance Analysis and Its Impact on Design.

Pradip Bose, Thomas M. Conte

Computer, 1998

Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures.

Emre Özer, Sanjeev Banerjia, Thomas M. Conte

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

Treegion Scheduling for Wide Issue Processors.

William A. Havanki, Sanjeev Banerjia, Thomas M. Conte

Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

Value Speculation Scheduling for High Performance Processors.

Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte

Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

A Fast Interrupt Handling Scheme for VLIW Processors.

Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte

Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997

Optimization of VLIW compatibility systems employing dynamic rescheduling.

Thomas M. Conte, Sumedh W. Sathaye

Int. J. Parallel Program., 1997

Compilers for Instruction-Level Parallelism.

Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson

Computer, 1997

Challenges to Combining General-Purpose and Multimedia Processors.

Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe

Computer, 1997

Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities.

Thomas M. Conte, Andrew Wolfe

Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

Treegion Scheduling for Highly Parallel Processors.

Sanjeev Banerjia, William A. Havanki, Thomas M. Conte

Proceedings of the Euro-Par '97 Parallel Processing, 1997

Path Prediction for High Issue-Rate Processors.

Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte

Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996

Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization.

Thomas M. Conte, Burzin A. Patel, Kishore N. Menezes, J. Stan Cox

Int. J. Parallel Program., 1996

Importance of Profiling and Compatibility.

Thomas M. Conte

ACM Comput. Surv., 1996

Bipartitioning for Hybrid FPGA-Software Simulatio.

Ashutosh Singla, Thomas M. Conte

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures.

Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Accurate and Practical Profile-driven Compilation Using the Profile Buffer.

Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.

Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

Reducing State Loss For Effective Trace Sampling of Superscalar Processors.

Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

Advances in Benchmarking Techniques: New Standards and Quantitative Metrics.

Thomas M. Conte, Wen-mei W. Hwu

Adv. Comput., 1995

Dynamic rescheduling: a technique for object code compatibility in VLIW architectures.

Thomas M. Conte, Sumedh W. Sathaye

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Optimization of Instruction Fetch Mechanisms for High Issue Rates.

Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

Commercializing profile-driven optimization.

J. Stan Cox, David P. Howell, Thomas M. Conte

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

A technique to determine power-efficient, high-performance superscalar processors.

Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994

The Susceptibility of Programs to Context Switching.

Wen-mei W. Hwu, Thomas M. Conte

IEEE Trans. Computers, 1994

Using branch handling hardware to support profile-driven optimization.

Thomas M. Conte, Burzin A. Patel, J. Stan Cox

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

Fast Simulation of Computer Architectures: Introduction.

Thomas M. Conte, Charles E. Gimarc

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993

The Effect of Code Expanding Optimizations on Instruction Cache Design.

William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu

IEEE Trans. Computers, 1993

Determining Cost-Effective Multiple Issue Processor Designs.

Thomas M. Conte, William H. Mangione-Smith

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992

Systematic Computer Architecture Prototyping

Thomas M. Conte

PhD thesis, 1992

Systematic prototyping of superscalar computer architectures.

Thomas M. Conte, Wen-mei W. Hwu

Proceedings of the Third International Workshop on Rapid System Prototyping, 1992

Tradeoffs in processor/memory interfaces for superscalar processors.

Thomas M. Conte

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1991

A brief survey of benchmark usage in the architecture community.

Thomas M. Conte, Wen-mei W. Hwu

SIGARCH Comput. Archit. News, 1991

Benchmark Characterization.

Thomas M. Conte, Wen-mei W. Hwu

Computer, 1991

1989

A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract).

Wen-mei W. Hwu, Thomas M. Conte

Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1989

Comparing Software and Hardware Schemes For Reducing the Cost of Branches.

Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1984

Thinwire protocol for connecting personal computers to the Internet.

David J. Farber, Gary S. Delp, Thomas M. Conte

RFC, September, 1984