Thomas Luinaud

Orcid: 0000-0003-4114-1179

According to our database1, Thomas Luinaud authored at least 8 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Symbolic Analysis for Data Plane Programs Specialization.
ACM Trans. Archit. Code Optim., March, 2023

2022
An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Design Principles for Packet Deparsers on FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020
Bridging the Gap: FPGAs as Programmable Switches.
Proceedings of the 21st IEEE International Conference on High Performance Switching and Routing, 2020

Unleashing the Power of FPGAs as Programmable Switches.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2018
One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing.
Proceedings of the 2018 IEEE 26th International Conference on Network Protocols, 2018

2017
An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017


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