Thomas Ludwig

According to our database, Thomas Ludwig authored at least 5 papers between 1997 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2004

Power-delay product minimization in high-performance 64-bit carry-select adders.

Amaury Nève, Helmut Schettler, Thomas Ludwig, Denis Flandre

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Scaling beyond the 65 nm node with FinFET-DGCMOS.

Edward J. Nowak, Thomas Ludwig, Ingo Aller, Jakub Kedzierski, M. Leong, BethAnn Rainey, Matthew J. Breitwisch, V. Gemhoefer, Joachim Keinert, David M. Fried

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.

Amaury Nève, Denis Flandre, Helmut Schettler, Thomas Ludwig, Gerhard Hellner

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1998

A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset.

Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger

Proceedings of the 1998 Design, 1998

1997

Standard-cell-based design methodology for high-performance support chips.

Bernhard Kick, Ulrich Baur, Jürgen Koehl, Thomas Ludwig, Thomas Pflueger

IBM J. Res. Dev., 1997