Thomas J. Snethen

According to our database, Thomas J. Snethen authored at least 13 papers between 1970 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Efficient testing of hierarchical core-based SOCs.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen

Proceedings of the 2014 International Test Conference, 2014

2010

Low cost at-speed testing using On-Product Clock Generation compatible with test compression.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test.

Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai

J. Low Power Electron., 2009

2007

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation.

Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise

Proceedings of the 2007 IEEE International Test Conference, 2007

Using Programmable On-Product Clock Generation (OPCG) for Delay Test.

Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen

Proceedings of the 16th Asian Test Symposium, 2007

2001

A SmartBIST Variant with Guaranteed Encoding.

Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999

A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor.

Xinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip.

Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Advanced microprocessor test strategy and methodology.

William V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko, Stephen Pateras, Dale E. Hoffman, Timothy G. McNamara, Thomas J. Snethen

IBM J. Res. Dev., 1997

1996

A weighted random pattern test generation system.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1994

Design of an Efficient Weighted-Random-Pattern Generation System.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1977

Simulator-oriented fault test generator.

Thomas J. Snethen

Proceedings of the 14th Design Automation Conference, 1977

1970

Minimizing the problem of logic testing by the interaction of a design group with user-oriented facilities.

Manuel Correia, Donald Cossman, Franco Putzolu, Thomas J. Snethen

Proceedings of the 7th Design Automation Workshop, 1970