Thomas J. Repetti
Orcid: 0000-0002-6866-8328
According to our database1,
Thomas J. Repetti
authored at least 5 papers
between 2017 and 2023.
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Bibliography
2023
Designing, Implementing and Programming a Massively Multithreaded Spatial Accelerator Architecture
PhD thesis, 2023
2020
Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things.
IEEE J. Solid State Circuits, 2020
2019
Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Master of none acceleration: a comparison of accelerator architectures for analytical query processing.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017