Thomas Haine

According to our database, Thomas Haine authored at least 6 papers between 2015 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.

David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre

IEEE J. Solid State Circuits, 2021

2019

A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.

David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics.

Thomas Haine, Johan Segers, Denis Flandre, David Bol

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.

Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016

CAMEL: An Ultra-Low-Power VGA CMOS Imager based on a Time-Based DPS Array.

Thomas Haine, François Stas, Guerric de Streel, Cecilia Gimeno, Denis Flandre, David Bol

Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

2015

Analysis and optimization for dynamic read stability in 28nm SRAM bitcells.

Ahmed T. Elthakeb, Thomas Haine, Denis Flandre, Yehea Ismail, Hamdy Abd Elhamid, David Bol

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015