Thomas Haine
Orcid: 0000-0001-8354-8095
According to our database1,
Thomas Haine
authored at least 6 papers
between 2015 and 2021.
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Collaborative distances:
Timeline
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Bibliography
2021
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.
IEEE J. Solid State Circuits, 2021
2019
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristics.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015