Thomas Fröhnel

According to our database, Thomas Fröhnel authored at least 3 papers between 2010 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.

Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.

Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 32nm 0.5V-supply dual-read 6T SRAM.

Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010