Thomas Edison Yu

According to our database, Thomas Edison Yu authored at least 7 papers between 2007 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC.

Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.

Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.

Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips.

Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths.

Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.

Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip.

Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara

Proceedings of the 16th Asian Test Symposium, 2007