Thomas Carle

According to our database, Thomas Carle authored at least 26 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

Verifying HyperLTL Properties in Event-B.

Jean-Paul Bodeveix, Thomas Carle, Elie Fares, Mamoun Filali, Thai Son Hoang

Proceedings of the Rigorous State-Based Methods - 10th International Conference, 2024

A Predictable SIMD Library for GEMM Routines.

Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Victor Jégu, Claire Pagetti

Proceedings of the 30th IEEE Real-Time and Embedded Technology and Applications Symposium, 2024

Modelling and proving the monotonicity of processor pipelines in Coq.

Alban Gruin, Armelle Bonenfant, Thomas Carle, Christine Rochange

Proceedings of the 22nd ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2024

Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUs.

Noïc Crouzet, Thomas Carle, Christine Rochange

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Parallelism and timing predictability in real-time systems.

Thomas Carle

, 2024

2023

Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources.

Zhenyu Bai, Hugues Cassé, Thomas Carle, Christine Rochange

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Extending a predictable machine learning framework with efficient gemm-based convolution routines.

Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Claire Pagetti

Real Time Syst., September, 2023

MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution.

Alban Gruin, Thomas Carle, Christine Rochange, Hugues Cassé, Pascal Sainrat

IEEE Trans. Computers, 2023

Warp-Level CFG Construction for GPU Kernel WCET Analysis.

Louison Jeanmougin, Pascal Sotin, Christine Rochange, Thomas Carle

Proceedings of the 21th International Workshop on Worst-Case Execution Time Analysis, 2023

Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators.

Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat

Proceedings of the 21th International Workshop on Worst-Case Execution Time Analysis, 2023

Enabling timing predictability in the presence of store buffers.

Alban Gruin, Thomas Carle, Christine Rochange, Pascal Sainrat

Proceedings of the 31st International Conference on Real-Time Networks and Systems, 2023

2022

A Framework for Calculating WCET Based on Execution Decision Diagrams.

Zhenyu Bai, Hugues Cassé, Marianne De Michiel, Thomas Carle, Christine Rochange

ACM Trans. Embed. Comput. Syst., 2022

ACETONE: Predictable Programming Framework for ML Applications in Safety-Critical Systems (Artifact).

Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Claire Pagetti

Dagstuhl Artifacts Ser., 2022

ACETONE: Predictable Programming Framework for ML Applications in Safety-Critical Systems.

Iryna De Albuquerque Silva, Thomas Carle, Adrien Gauffriau, Claire Pagetti

Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

Correctness and Efficiency Criteria for the Multi-Phase Task Model.

Rémi Meunier, Thomas Carle, Thierry Monteil

Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

2021

Speculative Execution and Timing Predictability in an Open Source RISC-V Core.

Alban Gruin, Thomas Carle, Hugues Cassé, Christine Rochange

Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Static Extraction of Memory Access Profiles for Multi-core Interference Analysis of Real-Time Tasks.

Thomas Carle, Hugues Cassé

Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021

2020

Improving the Performance of WCET Analysis in the Presence of Variable Latencies.

Zhenyu Bai, Hugues Cassé, Marianne De Michiel, Thomas Carle, Christine Rochange

Proceedings of the 21st ACM SIGPLAN/SIGBED International Conference on Languages, 2020

2018

Reducing Timing Interferences in Real-Time Applications Running on Multicore Architectures.

Thomas Carle, Hugues Cassé

Proceedings of the 18th International Workshop on Worst-Case Execution Time Analysis, 2018

2016

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.

Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar

Proceedings of the 2016 International Conference on Compilers, 2016

2015

From Dataflow Specification to Multiprocessor Partitioned Time-triggered Real-time Implementation.

Thomas Carle, Dumitru Potop-Butucaru, Yves Sorel, David Lesens

Leibniz Trans. Embed. Syst., 2015

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling.

Raul Gorcitz, Emilien Kofman, Thomas Carle, Dumitru Potop-Butucaru, Robert de Simone

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2015

2014

Compilation efficace de spécifications de contrôle embarqué avec prise en compte de propriétés fonctionnelles et non-fonctionnelles complexes. (Efficient compilation of embedded control specifications with complex functional and non-functional properties).

Thomas Carle

PhD thesis, 2014

Predicate-aware, makespan-preserving software pipelining of scheduling tables.

Thomas Carle, Dumitru Potop-Butucaru

ACM Trans. Archit. Code Optim., 2014

Reconciling performance and predictability on a many-core through off-line mapping.

Thomas Carle, Manel Djemal, Daniela Genius, François Pêcheux, Dumitru Potop-Butucaru, Robert de Simone, Franck Wajsbürt, Zhen Zhang

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays.

Thomas Carle, Manel Djemal, Dumitru Potop-Butucaru, Robert de Simone, Zhen Zhang

Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014