Thomas Bourgeat

Orcid: 0000-0002-8468-8409

According to our database1, Thomas Bourgeat authored at least 26 papers between 2014 and 2025.

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Bibliography

2025
CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches.
IEEE Des. Test, February, 2025

2024
Formal Verification for Secure Processors: A Guide for Computer Architects.
Computer, October, 2024

RTL Verification for Secure Speculation Using Contract Shadow Logic.
CoRR, 2024

Parendi: Thousand-Way Parallel RTL Simulation.
CoRR, 2024

Performance Interfaces for Hardware Accelerators.
Proceedings of the 18th USENIX Symposium on Operating Systems Design and Implementation, 2024

Verifying Software Emulation of an Unsupported Hardware Instruction.
Proceedings of the 15th International Conference on Interactive Theorem Proving, 2024

Specification and Verification of Strong Timing Isolation of Hardware Enclaves.
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024

2023
Flexible Instruction-Set Semantics via Abstract Monads (Experience Report).
Proc. ACM Program. Lang., August, 2023

Specification and verification of sequential machines in rule-based hardware languages
PhD thesis, 2023

Citadel: Side-Channel-Resistant Enclaves with Secure Shared Memory on a Speculative Out-of-Order Processor.
CoRR, 2023

Pensieve: Microarchitectural Modeling for Security Evaluation.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

RoboShape: Using Topology Patterns to Scalably and Flexibly Deploy Accelerators Across Robots.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
DAGguise: mitigating memory timing side channels.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Accelerating Robot Dynamics Gradients on a CPU, GPU, and FPGA.
IEEE Robotics Autom. Lett., 2021

A Multipurpose Formal RISC-V Specification.
CoRR, 2021

FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Effective simulation and debugging for a high-level hardware language using software compilers.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Robomorphic computing: a design methodology for domain-specific accelerators parameterized by robot morphology.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
The essence of Bluespec: a core language for rule-based hardware design.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

AQUOMAN: An Analytic-Query Offloading Machine.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

2019
Composable Building Blocks to Open Up Processor Design.
IEEE Micro, 2019

MI6: Secure Enclaves in a Speculative Out-of-Order Processor.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018
Composable Building Blocks to Open up Processor Design.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2016
Specification Mining for Asynchronous Controllers.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2014
New Algorithmic Approaches to Point Constellation Recognition.
Proceedings of the ICT Systems Security and Privacy Protection, 2014


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