Thomas Benz
Orcid: 0000-0002-0326-9676
According to our database1,
Thomas Benz
authored at least 24 papers
between 1985 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Computers, January, 2024
ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package.
CoRR, 2024
CoRR, 2024
CoRR, 2024
Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design?
CoRR, 2024
Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC.
CoRR, 2024
Data-Driven Power Modeling and Monitoring via Hardware Performance Counters Tracking.
CoRR, 2024
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the 2024 USENIX Annual Technical Conference, 2024
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
2023
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE Trans. Computers, 2022
A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous Platforms.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
2021
A RISC-V in-network accelerator for flexible high-performance low-power packet processing.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
CoRR, 2020
2011
Proceedings of the IEEE Intelligent Vehicles Symposium (IV), 2011
2010
The impact of traffic-light-to-vehicle communication on fuel consumption and emissions.
Proceedings of the 2010 Internet of Things (IOT), IoT for a green Planet, Tokyo, Japan, November 29, 2010
1993
J. Intell. Transp. Syst., 1993
1985
Mikroskopische Simulation von Energieverbrauch und Abgasemission im Strassenverkehr (MISEVA).
PhD thesis, 1985