Thomas B. Rolinger

Orcid: 0000-0001-8383-4737

According to our database1, Thomas B. Rolinger authored at least 18 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
TLPGNN: A Lightweight Two-level Parallelism Paradigm for Graph Neural Network Computation on Single and Multiple GPUs.
ACM Trans. Parallel Comput., June, 2024

Adaptive Prefetching for Fine-grain Communication in PGAS Programs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

JITSPMM: Just-in-Time Instruction Generation for Accelerated Sparse Matrix-Matrix Multiplication.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023
Compiler Optimizations for Irregular Memory Access Patterns in the PGAS Programming Model.
PhD thesis, 2023

Decontentioned Stochastic Block Partition.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023

2022
Compiler Optimization for Irregular Memory Access Patterns in PGAS Programs.
Proceedings of the Languages and Compilers for Parallel Computing, 2022

2021
Towards High Productivity and Performance for Irregular Applications in Chapel.
Proceedings of the 2021 SC Workshops Supplementary Proceedings, 2021

Optimizing Memory-Compute Colocation for Irregular Applications on a Migratory Thread Architecture.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Faster Stochastic Block Partition Using Aggressive Initial Merging, Compressed Representation, and Parallelism Control.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

2020
Performance Strategies for Parallel Bitonic Sort on a Migratory Thread Architecture.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019
Performance considerations for scalable parallel tensor decomposition.
J. Parallel Distributed Comput., 2019

Optimizing Data Layouts for Irregular Applications on a Migratory Thread Architecture.
Proceedings of the 2019 IEEE/ACM Workshop on Memory Centric High Performance Computing, 2019

2018
Impact of Traditional Sparse Optimizations on a Migratory Thread Architecture.
Proceedings of the 8th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2018

Parallel Sparse Tensor Decomposition in Chapel.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Exploring Parallel Bitonic Sort on a Migratory Thread Architecture.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

An Empirical Evaluation of Allgatherv on Multi-GPU Systems.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018

2017
Performance challenges for heterogeneous distributed tensor decompositions.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016
Performance Evaluation of Parallel Sparse Tensor Decomposition Implementations.
Proceedings of the 6th Workshop on Irregular Applications: Architecture and Algorithms, 2016


  Loading...