Thomas A. Ziaja

According to our database, Thomas A. Ziaja authored at least 10 papers between 1994 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2012

Sparc T4: A Dynamically Threaded Server-on-a-Chip.

Manish K. Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja

IEEE Micro, 2012

2009

Efficient Array Characterization in the UltraSPARC T2.

Thomas A. Ziaja, Poh J. Tan

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008

Transition Test on UltraSPARC- T2 Microprocessor.

Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip.

Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh

Proceedings of the 2007 IEEE International Test Conference, 2007

2002

A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC^TM Chip Multi-Processors.

Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.

Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1999

Using LSSD to test modules at the board level.

Thomas A. Ziaja

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1996

Comprehensive Modeling of VLSI Test.

Thomas A. Ziaja, Earl E. Swartzlander Jr.

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Characterization and analysis of errors in circuit test.

Thomas A. Ziaja, Earl E. Swartzlander Jr.

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994

Boundary scan in board manufacturing.

Thomas A. Ziaja, Earl E. Swartzlander Jr.

J. Electron. Test., 1994