Thiruvengadam Vijayaraghavan

According to our database, Thiruvengadam Vijayaraghavan authored at least 3 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

MPU-BWM: Accelerating Sequence Alignment.

Thiruvengadam Vijayaraghavan, Amit Rajesh, Karthikeyan Sankaralingam

IEEE Comput. Archit. Lett., 2018

2017

Design and Analysis of an APU for Exascale Computing.

Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2015

ISA Wars: Understanding the Relevance of ISA being RISC or CISC to Performance, Power, and Energy on Modern Architectures.

Emily R. Blem, Jaikrishnan Menon, Thiruvengadam Vijayaraghavan, Karthikeyan Sankaralingam

ACM Trans. Comput. Syst., 2015