Thilo Pionteck
Orcid: 0000-0001-6518-1226Affiliations:
- University of Lübeck, Germany
According to our database1,
Thilo Pionteck
authored at least 114 papers
between 2000 and 2024.
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Collaborative distances:
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Bibliography
2024
Proceedings of the 19th International Joint Conference on Computer Vision, 2024
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024
Proceedings of the Architecture of Computing Systems - 37th International Conference, 2024
2023
Hybrid CPU/GPU/APU accelerated query, insert, update and erase operations in hash tables with string keys.
Knowl. Inf. Syst., October, 2023
Distributed Parallel Databases, September, 2023
A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units.
Concurr. Comput. Pract. Exp., 2023
IEEE Access, 2023
Proceedings of the 39th IEEE International Conference on Data Engineering, 2023
A Flexible and Scalable Reconfigurable FPGA Overlay Architecture for Data-Flow Processing.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023
What Happens When Two Multi-Query Optimization Paradigms Combine? - A Hybrid Shared Sub-Expression (SSE) and Materialized View Reuse (MVR) Study.
Proceedings of the Advances in Databases and Information Systems, 2023
2022
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs.
ACM Trans. Model. Comput. Simul., 2022
Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022
Proceedings of the Database and Expert Systems Applications, 2022
Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022
2021
Datenbank-Spektrum, 2021
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021
An Investigation of Atomic Synchronization for Sort-Based Group-By Aggregation on GPUs.
Proceedings of the 37th IEEE International Conference on Data Engineering Workshops, 2021
Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
2020
J. Supercomput., 2020
Proceedings of the 28th Italian Symposium on Advanced Database Systems, 2020
Hardware/Software Co-Design of a control and data acquisition system for Computed Tomography.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020
Proceedings of the International Conference on Field-Programmable Technology, 2020
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
Proceedings of the International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2020
2019
Simulation environment for link energy estimation in networks-on-chip with virtual channels.
Integr., 2019
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment.
Integr., 2019
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs.
CoRR, 2019
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures.
IEEE Access, 2019
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
Cooking DBMS Operations using Granular Primitives - An Overview on a Primitive-based RDBMS Query Evaluation.
Datenbank-Spektrum, 2018
Datenbank-Spektrum, 2018
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
Proceedings of the 30th GI-Workshop Grundlagen von Datenbanken, Wuppertal, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
2017
Microprocess. Microsystems, 2017
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs.
Microprocess. Microsystems, 2017
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017
2016
ACM Trans. Reconfigurable Technol. Syst., 2016
Open J. Big Data, 2016
Concurr. Comput. Pract. Exp., 2016
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Adaptive allocation of default router paths in Network-on-Chips for latency reduction.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
2015
Open J. Databases, 2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs.
Proceedings of the Nordic Circuits and Systems Conference, 2015
2014
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases.
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014
2013
Register allocation for high-level synthesis of hardware accelerators targeting FPGAs.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the International Conference on High Performance Computing & Simulation, 2013
Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013
2012
Proceedings of the ROBOTIK 2012, 2012
An Approach for Performance Estimation of Hybrid Systems with FPGAs and GPUs as Coprocessors.
Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012
2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
2010
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010
A concept of a trust management architecture to increase the robustness of nano age devices.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010
2009
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime.
Int. J. Reconfigurable Comput., 2009
2008
Parallel Process. Lett., 2008
Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, 2008
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Proceedings of the FPL 2008, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2007
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme).
it Inf. Technol., 2007
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
2006
Eine Scheduling Heuristik zur Minimierung der Verlustleistung.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
Proceedings of the Embedded Computer Systems: Architectures, 2005
Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005
2004
Design of a reconfigurable AES encryption/decryption engine for mobile terminals.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.
Proceedings of the Field Programmable Logic and Application, 2004
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
Proceedings of the ARCS 2004, 2004
2003
Des. Autom. Embed. Syst., 2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
2002
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.
Proceedings of the Field-Programmable Logic and Applications, 2001
2000
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
Proceedings of the Field-Programmable Logic and Applications, 2000