Thilini Kaushalya Bandara

Orcid: 0000-0003-3413-136X

According to our database1, Thilini Kaushalya Bandara authored at least 5 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Flip: Data-centric Edge CGRA Accelerator.
ACM Trans. Design Autom. Electr. Syst., January, 2024

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024

2023
FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

REVAMP: a systematic framework for heterogeneous CGRA realization.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022


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