Thierry Grandpierre
Orcid: 0000-0002-7239-581X
According to our database1,
Thierry Grandpierre
authored at least 24 papers
between 1999 and 2024.
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Bibliography
2024
Proceedings of the 27th IEEE International Symposium on Real-Time Distributed Computing, 2024
Latency-Accurate Models for Software Programmable Streaming Coarse-Grained Reconfigurable Hardware Architectures.
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024
Adéquation Algorithme Architecture : Modélisations, Implémentations, Optimisations pour Applications Temps Réel Embarquées.
, 2024
2019
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019
Proceedings of the IEEE International Conference on Pervasive Computing and Communications Workshops, 2019
2017
Embedded Real-Time H264/AVC High Definition Video Encoder on TI's KeyStone Multicore DSP.
J. Signal Process. Syst., 2017
2016
Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera.
J. Real Time Image Process., 2016
2015
J. Real Time Image Process., 2015
2014
Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014
2012
J. Real Time Image Process., 2012
2010
Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices.
Neural Comput. Appl., 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2008
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2008
2007
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007
2006
FPGA-based architecture for hardware compression/decompression of wide format images.
J. Real Time Image Process., 2006
A rapid prototyping methodology to implement and optimize image processing algorithms for FPGAs.
Proceedings of the Real-Time Image Processing 2006, San Jose, CA, USA, January 15, 2006, 2006
2004
J. Supercomput., 2004
AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits.
Proceedings of the Field Programmable Logic and Application, 2004
2003
From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003
From Algorithm Graph Specification to Automatic Synthesis of FPGA Circuit: A Seamless Flow of Graphs Transformations.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
A Methodology to Implement Real-Time Applications on Reconfigurable Circuits.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003
2000
Proceedings of the 2000 International Conference on Compilers, 2000
1999
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999