Thierry Di Gilio

According to our database, Thierry Di Gilio authored at least 4 papers between 2013 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI.

Guenole Lallement, Fady Abouzeid, Thierry Di Gilio, Philippe Roche, Jean-Luc Autran

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2016

Temperature-based adaptive memory sub-system in 28nm UTBB FDSOI.

Amit Chhabra, Mudit Srivastava, Prakhar Raj Gupta, Kedar Janardan Dhori, Philippe Triolet, Thierry Di Gilio, Nitin Bansal, B. Sujatha

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.

David Jacquet, Frederic Hasbani, Philippe Flatresse, Robin Wilson, Franck Arnaud, Giorgio Cesana, Thierry Di Gilio, Christophe Lecocq, Tanmoy Roy, Amit Chhabra, Chiranjeev Grover, Olivier Minez, Jacky Uginet, Guy Durieu, Cyril Adobati, Davide Casalotto, Frederic Nyer, Patrick Menut, Andreia Cathelin, Indavong Vongsavady, Philippe Magarshack

IEEE J. Solid State Circuits, 2014

2013

Black box small-signal model of PMOS LDO voltage regulator.

Thomas Souvignet, Thomas Coulot, Yann David, Severin Trochut, Thierry Di Gilio, Bruno Allard

Proceedings of the IECON 2013, 2013