Thierry Bonnoit

According to our database, Thierry Bonnoit authored at least 8 papers between 2011 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance.

Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis

IEEE Trans. Very Large Scale Integr. Syst., 2018

Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solution.

Thierry Bonnoit, Fraidy Bouesse, Nacer-Eddine Zergainoh, Michael Nicolaidis

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core.

Thierry Bonnoit, Alexandre Coelho, Nacer-Eddine Zergainoh, Raoul Velazco

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Low cost rollback to improve fault-tolerance in VLSI circuits.

Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis, Raoul Velazco

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2014

Robust BER estimator for DBPSK modulation.

Thierry Bonnoit, Dominique Morche, Cedric Dehos, Emeric de Foucauld

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013

Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study.

Thierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh

J. Electron. Test., 2013

2011

Towards a tool for implementing delay-free ECC in embedded memories.

Thierry Bonnoit, Michael Nicolaidis, Nacer-Eddine Zergainoh

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Eliminating speed penalty in ECC protected memories.

Michael Nicolaidis, Thierry Bonnoit, Nacer-Eddine Zergainoh

Proceedings of the Design, Automation and Test in Europe, 2011