Thiago Copetti
Orcid: 0000-0001-7591-6484
According to our database1,
Thiago Copetti
authored at least 31 papers
between 2012 and 2024.
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Bibliography
2024
J. Electron. Test., April, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
2021
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.
J. Electron. Test., 2021
J. Electron. Test., 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
2020
Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects.
J. Electron. Test., 2020
Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.
Proceedings of the IEEE Latin-American Test Symposium, 2020
2019
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects.
J. Electron. Test., 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
2018
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
2017
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
2016
J. Electron. Test., 2016
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time.
J. Electron. Test., 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
Proceedings of the 15th Latin American Test Workshop, 2014
2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012