Thi Hong Tran

Orcid: 0000-0002-2744-0079

According to our database1, Thi Hong Tran authored at least 45 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2023
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications.
IEEE Des. Test, October, 2023

A Decentralized COVID-19 Vaccine Tracking System Using Blockchain Technology.
Cryptogr., March, 2023

Hardware-Based Architecture for DNN Wireless Communication Models.
Sensors, February, 2023

Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing.
Proceedings of the International Conference on Computing and Communication Technologies, 2023

Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms.
Proceedings of the 15th International Conference on Knowledge and Systems Engineering, 2023

Robust Deep Learning Approaches for Wireless Communication Systems.
Proceedings of the 2023 11th International Conference on Information Technology: IoT and Smart City, 2023

Optimizing Parkinson's Disease Classification and Severity Assessment Using Dense Multiscale Sample Entropy and Hybrid Feature Selection.
Proceedings of the 2023 11th International Conference on Information Technology: IoT and Smart City, 2023

Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications.
Proceedings of the International Conference on IC Design and Technology, 2023

Efficient and High-Speed CGRA Accelerator for Cryptographic Applications.
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023

2022
Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator.
IEEE Access, 2022

A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator.
IEEE Access, 2022

A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021
BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A High-Performance Multimem SHA-256 Accelerator for Society 5.0.
IEEE Access, 2021

MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security.
IEEE Access, 2021

High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021

2020
Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining.
IEEE Access, 2020

2019
Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems.
CoRR, 2019

Hardware Implementation of the Efficient SOR-Based Massive MIMO Detection for Uplink.
Proceedings of the 2019 IEEE-RIVF International Conference on Computing and Communication Technologies, 2019

Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah.
Proceedings of the 7th International Conference on Communications and Broadband Networking, 2019

Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2019

Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach.
Proceedings of the 25th Asia-Pacific Conference on Communications, 2019

2018
Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver.
CoRR, 2018

A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract.
Proceedings of the IEEE Globecom Workshops, 2018

2017
A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes.
J. Commun., 2017

2016
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

ASIC design of a low-complexity K-best Viterbi decoder for IoT applications.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2014
Algorithm and hardware design of a 2D sorter-based K-best MIMO decoder.
EURASIP J. Wirel. Commun. Netw., 2014

A 2D Sorter-Based K-Best Algorithm for High Order Modulation MIMO Systems.
Proceedings of the IEEE 80th Vehicular Technology Conference, 2014

ASIC design of 7.7 Gbps multi-mode LDPC decoder for IEEE 802.11ac.
Proceedings of the 14th International Symposium on Communications and Information Technologies, 2014

A 4 × 4 multiplier-divider-less K-best MIMO decoder up to 2.7 Gbps.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A design of low complex log likelihood ratio for MIMO decoder using the bit shift.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Hardware Design of Multi Gbps RC4 Stream Cipher.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012
Hardware Implementation of High Throughput RC4 algorithm.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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