Thi Hong Tran

According to our database, Thi Hong Tran authored at least 45 papers between 2012 and 2024.

Collaborative distances:

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2024

Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications.

Vu Trung Duong Le, Hoai-Luan Pham, Thi Hong Tran, Yasuhiko Nakashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements.

Pham Hoai Luan, Hai Hau Nguyen, Vu Trung Duong Le, Thi Diem Tran, Tuan Hai Vu, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2023

Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications.

Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima

IEEE Des. Test, October, 2023

A Decentralized COVID-19 Vaccine Tracking System Using Blockchain Technology.

Atsuki Koyama, Van Chuong Tran, Manato Fujimoto, Vo Nguyen Quoc Bao, Thi Hong Tran

Cryptogr., March, 2023

Hardware-Based Architecture for DNN Wireless Communication Models.

Van Duy Tran, Duc Khai Lam, Thi Hong Tran

Sensors, February, 2023

Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing.

Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing.

Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Ren Imamura, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the International Conference on Computing and Communication Technologies, 2023

Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain.

Pham Hoai Luan, Thi Sang Duong, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing.

Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission.

Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms.

Vu Trung Duong Le, Hoai Luan Pham, Thi Sang Duong, Thi Hong Tran, Quoc Duy Nam Nguyen, Yasuhiko Nakashima

Proceedings of the 15th International Conference on Knowledge and Systems Engineering, 2023

Robust Deep Learning Approaches for Wireless Communication Systems.

Van Duy Tran, Duc Khai Lam, Thi Hong Tran

Proceedings of the 2023 11th International Conference on Information Technology: IoT and Smart City, 2023

Optimizing Parkinson's Disease Classification and Severity Assessment Using Dense Multiscale Sample Entropy and Hybrid Feature Selection.

Quoc Duy Nam Nguyen, Thi Hong Tran, Tadashi Nakano

Proceedings of the 2023 11th International Conference on Information Technology: IoT and Smart City, 2023

Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications.

Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Quoc Duy Nam Nguyen, Thi Sang Duong, Yasuhiko Nakashima

Proceedings of the International Conference on IC Design and Technology, 2023

Efficient and High-Speed CGRA Accelerator for Cryptographic Applications.

Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima

Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023

2022

Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator.

Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima

IEEE Access, 2022

A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator.

Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima

IEEE Access, 2022

A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications.

Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima

Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining.

Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks.

Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration.

Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021

BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks.

Thi Hong Tran, Hoai Luan Pham, Tri Dung Phan, Yasuhiko Nakashima

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A High-Performance Multimem SHA-256 Accelerator for Society 5.0.

Thi Hong Tran, Hoai Luan Pham, Yasuhiko Nakashima

IEEE Access, 2021

MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security.

Vu Trung Duong Le, Thi Hong Tran, Hoai Luan Pham, Duc Khai Lam, Yasuhiko Nakashima

IEEE Access, 2021

High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory.

Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021

2020

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining.

Hoai Luan Pham, Thi Hong Tran, Tri Dung Phan, Vu Trung Duong Le, Duc Khai Lam, Yasuhiko Nakashima

IEEE Access, 2020

2019

Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems.

Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Yasuhiko Nakashima

CoRR, 2019

Hardware Implementation of the Efficient SOR-Based Massive MIMO Detection for Uplink.

Chong Nhat Cuong, Thi Hong Tran, Duc Khai Lam

Proceedings of the 2019 IEEE-RIVF International Conference on Computing and Communication Technologies, 2019

Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah.

Dai Long Hoang, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the 7th International Conference on Communications and Broadband Networking, 2019

Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract.

Van-Cam Nguyen, Hoai-Luan Pham, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima

Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2019

Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach.

Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the 25th Asia-Pacific Conference on Communications, 2019

2018

Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems.

Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver.

Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima

CoRR, 2018

A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract.

Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the IEEE Globecom Workshops, 2018

2017

A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes.

Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima

J. Commun., 2017

2016

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis.

Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system.

Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima

Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

ASIC design of a low-complexity K-best Viterbi decoder for IoT applications.

Hiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2014

Algorithm and hardware design of a 2D sorter-based K-best MIMO decoder.

Thi Hong Tran, Yuhei Nagao, Hiroshi Ochi

EURASIP J. Wirel. Commun. Netw., 2014

A 2D Sorter-Based K-Best Algorithm for High Order Modulation MIMO Systems.

Thi Hong Tran, Hiroshi Ochi, Yuhei Nagao

Proceedings of the IEEE 80th Vehicular Technology Conference, 2014

ASIC design of 7.7 Gbps multi-mode LDPC decoder for IEEE 802.11ac.

Thi Hong Tran, Yuhei Nagao, Hiroshi Ochi, Masayuki Kurosaki

Proceedings of the 14th International Symposium on Communications and Information Technologies, 2014

A 4 × 4 multiplier-divider-less K-best MIMO decoder up to 2.7 Gbps.

Thi Hong Tran, Hiroshi Ochi, Yuhei Nagao

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A design of low complex log likelihood ratio for MIMO decoder using the bit shift.

Reina Hongyo, Thi Hong Tran, Leonardo Lanante, Hiroshi Ochi, Yuhei Nagao

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Hardware Design of Multi Gbps RC4 Stream Cipher.

Thi Hong Tran, Leonardo Lanante, Yuhei Nagao, Hiroshi Ochi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012

Hardware Implementation of High Throughput RC4 algorithm.

Thi Hong Tran, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012