Themistoklis Haniotakis

According to our database, Themistoklis Haniotakis authored at least 70 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations.

Sakib Mohammad, Themistoklis Haniotakis

CoRR, 2024

2020

A Built In Test circuit for waveform classification at high frequencies.

Konstantinos Poulos, Themistoklis Haniotakis

Proceedings of the 29th IEEE North Atlantic Test Workshop, 2020

ARIAN: A Scalable Method for Adding aRbItrAry Numbers on Modern Processors.

Konstantinos Poulos, Iraklis Anagnostopoulos, Themistoklis Haniotakis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model.

Theodoros Simopoulos, George Alexiou, Themistoklis Haniotakis

J. Circuits Syst. Comput., 2019

Power efficient synchronous counter design.

Raghava Katreepalli, Themistoklis Haniotakis

Comput. Electr. Eng., 2019

2018

A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions.

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 1Kx32 bit WDSRAM page with rapid write access.

Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

Delay Analysis for Current Mode Threshold Logic Gate Designs.

Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas

IEEE Trans. Very Large Scale Integr. Syst., 2017

More Efficient Testing of Metal-Oxide Memristor-Based Memory.

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An enhanced approach to reduce test application time through limited shift operations in scan chains.

Konstantinos Poulos, Jayasurya Kuchi, Themistoklis Haniotakis

Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

High Speed Power Efficient Carry Select Adder Design.

Raghava Katreepalli, Themistoklis Haniotakis

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Reducing power, area, and delay of threshold logic gates considering non-integer weights.

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A new method to identify threshold logic functions.

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

ATPG for Delay Defects in Current Mode Threshold Logic Circuits.

Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design.

Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Identification of delay defects on embedded paths using one current sensor.

Wisam Aljubouri, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015

A current monitoring technique for I_DDQ testing in digital integrated circuits.

Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Integr., 2015

Fast march tests for defects in resistive memory.

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

2014

Implementation of a Low Leakage Standard Cell Library based on materials from UMC 65nm technology.

Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

ATPG for transition faults of pipelined threshold logic circuits.

Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Diagnosis of segment delay defects with current sensing.

Wisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

Low power and high speed current-mode memristor-based TLGs.

Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission.

Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas

Ad Hoc Networks, 2012

Delay Analysis for an N-Input Current Mode Threshold Logic Gate.

Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011

A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate.

Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010

A Data Capturing Method for Buses on Chip.

Michael N. Skoufis, Kedar Karmarkar, Spyros Tragoudas, Themistoklis Haniotakis

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Memory-Less Pipeline Dynamic Circuit Design Technique.

Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2008

A Current Mode, Parallel, Two-Rail Code Checker.

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni

IEEE Trans. Computers, 2008

A High-Performance Bus Architecture for Strongly Coupled Interconnects.

Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

A Methodology for Transistor-Efficient Supergate Design.

Dimitrios Kagaris, Themistoklis Haniotakis

IEEE Trans. Very Large Scale Integr. Syst., 2007

Testable Designs of Multiple Precharged Domino Circuits.

Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou

IEEE Trans. Very Large Scale Integr. Syst., 2007

Glitch Control with Dynamic Receiver Threshold Adjustment.

Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Transistor-Level Synthesis for Low-Power Applications.

Dimitri Kagaris, Themistoklis Haniotakis

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

A Design Technique for Energy Reduction in NORA CMOS Logic.

Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Transistor-Level Optimization of Supergates.

Dimitri Kagaris, Themistoklis Haniotakis

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An Improved Method for Identifying Linear Dependencies in Path Delay Faults.

Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism.

Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

The Use of Pre-Evaluation Phase in Dynamic CMOS Logic.

A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Design and Evaluation of a Security Scheme for Sensor Networks.

Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Reduced Test Application Time Based on Reachability Analysis.

Themistoklis Haniotakis, Spyros Tragoudas, G. Pani

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Fast, Parallel Two-Rail Code Checker with Enhanced Testability.

Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

An embedded IDDQ testing circuit and technique.

Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 12th IEEE International Conference on Electronics, 2005

A security protocol for sensor networks.

Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

A built-in I_DDQ testing circuit.

Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

A unified framework for generating all propagation functions for logic errors and events.

Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs.

Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

J. Electron. Test., 2004

Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications .

Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.

A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Security enhancement through multiple path transmission in ad hoc networks.

Themistoklis Haniotakis, Spyros Tragoudas, Constantinos Kalapodas

Proceedings of IEEE International Conference on Communications, 2004

2003

An Embedded IDDQ Testing Architecture and Technique.

Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs.

Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A low power NORA circuit design technique based on charge recycling.

Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002

A new technique for IDDQ testing in nanometer technologies.

Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni

Integr., 2002

Extending the Viability of IDDQ Testing in the Deep Submicron Era.

Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology.

A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing.

Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001

Concurrent Detection of Soft Errors Based on Current Monitoring.

Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

New test pattern generation units for NPSF oriented memory built-in self test.

A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

On Testability of Multiple Precharged Domino Logic.

Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A Compact Built-In Current Sensor for IDDQ Testing.

Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

New memory sense amplifier designs in CMOS technology.

Y. Tsiatouhas, A. Chrisanthopoulos, George Kamoulakos, Th. Haniotakis

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A state assignment algorithm for finite state machines.

Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A Versatile Built-In Self-Test Scheme for Delay Fault Testing.

Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos

Proceedings of the 2000 Design, 2000

1999

Novel domino logic designs.

Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

On Path Delay Fault Testing of Multiplexer - Based Shifters.

Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing.

Y. Tsiatouhas, Th. Haniotakis

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks.

Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas

Proceedings of the 1999 Design, 1999

1998

C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.

Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1995

Efficient Totally Self-Checking Checkers for a Class of Borden Codes.

Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos

IEEE Trans. Computers, 1995

An efficient comparative concurrent Built-In Self-Test technique.

Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995