Tetsuyuki Suzaki

According to our database, Tetsuyuki Suzaki authored at least 5 papers between 1992 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1996

A 2.4 Gb/s receiver and a 1: 16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor.

Fumihiko Sato, Hiroshi Tezuka, Masaaki Soda, Takasuke Hashimoto, Tetsuyuki Suzaki, Tom Tatsumi, Takenori Morikawa, Tsutomu Tashiro

IEEE J. Solid State Circuits, 1996

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology.

Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida

IEEE J. Solid State Circuits, 1996

1994

Si-analog IC's for 20 Gb/s optical receiver.

Masaaki Soda, Hiroshi Tezuka, Fumihiko Sato, Takasuke Hashimoto, Satoshi Nakamura, Tom Tatsumi, Tetsuyuki Suzaki, Tsutomu Tashiro

IEEE J. Solid State Circuits, December, 1994

1992

Si bipolar chip set for 10-Gb/s optical receiver.

Tetsuyuki Suzaki, Masaaki Soda, Takenori Morikawa, Hiroshi Tezuka, Chihiro Ogawa, Sadao Fujita, Hisashi Takemura, Tsutomu Tashiro

IEEE J. Solid State Circuits, December, 1992

Pseudomorphic 2DEG FET IC's for 10 Gb/s optical communication systems with external optical modulation.

Yasuyuki Suzuki, Tetsuyuki Suzaki, Yumi Ogawa, Sadao Fujita, Wendy Liu, Akihiko Okamoto

IEEE J. Solid State Circuits, October, 1992