Tetsuya Yamada

According to our database1, Tetsuya Yamada authored at least 24 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Finishing Speed Improvement Using Side Cover Plates in Gyro Finishing.
Int. J. Autom. Technol., January, 2023

2021
Boundedness of solutions to a parabolic attraction-repulsion chemotaxis system in R2: The attractive dominant case.
Appl. Math. Lett., 2021

2020
Dielecrophoretic introduction of the membrane proteins into the BLM platforms for the electrophygiological analysis systems.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020

2019
Quantitative signal analysis of a ligand-gated ion channel on a lipid bilayer using continuous-time wavelet transformation.
Proceedings of the International Symposium on Micro-NanoMechatronics and Human Science, 2019

Artificial cell membrane system for odorant sensor: development of solution exchange driven by superabsorbent polymer for repeatable detection.
Proceedings of the IEEE International Symposium on Olfaction and Electronic Nose, 2019

2013
Hardware support for resource partitioning in real-time embedded systems.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

2012
IT-Cooling Collaborative Control Methods for Battery-Aware IT-Systems Targeting India.
Proceedings of the ICT as Key Technology against Global Warming, 2012

Battery-Aware IT Control Method for Effective Battery Use During Power Outage.
Proceedings of the 2012 IEEE International Conference on Green Computing and Communications, 2012

2011
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.
IEICE Trans. Electron., 2011

Beacon Tracking System and Its Performance in Search Operation for Hayabusa Sample Return Capsule.
IEICE Trans. Commun., 2011

2010

2008
Search for Alternatives and Collaboration with Incumbents: Two-Sided Sourcing Behavior in Business Markets.
Decis. Sci., 2008

2007
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
IEEE J. Solid State Circuits, 2007

A Hardware Accelerator for Java<sup>TM</sup> Platforms on a 130-nm Embedded Processor Core.
IEICE Trans. Electron., 2007

Embedded SoC Resource Manager to Control Temperature and Data Bandwidth.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Development of processor cores for digital consumer appliances.
Syst. Comput. Jpn., 2006

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.
IEICE Trans. Electron., 2006

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Low-Power Design of 90-nm SuperH Processor Core.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2002
Application of phased-array antenna technology to the 21 GHz broadcasting satellite for rain-attenuation compensation.
Proceedings of the IEEE International Conference on Communications, 2002

1996
On the Computational Power of Binary Decision Diagram with Redundant Variables.
Formal Methods Syst. Des., 1996

1995
An algorithm for speech parameter generation from continuous mixture HMMs with dynamic features.
Proceedings of the Fourth European Conference on Speech Communication and Technology, 1995


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