Tetsuya Uemura

According to our database, Tetsuya Uemura authored at least 12 papers between 1990 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2007

Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions.

Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2005

Clinical support system using information aggregation and visualization for order data.

Shuichi Toyoda, Noboru Niki, Tetsuya Uemura, Hiromu Nishitani

Syst. Comput. Jpn., 2005

Four-Valued Magnetic Random Access Memory Based on Magneto Tunnel Junction and Resonant Tunneling Diode.

Tetsuya Uemura, Masafumi Yamamoto

J. Multiple Valued Log. Soft Comput., 2005

2003

Proposal of Four-Valued MRAM based on MTJ/RTD Structure.

Tetsuya Uemura, Masafumi Yamamoto

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002

Rise time analysis of MOBILE circuit.

Tetsuya Uemura, Pinaki Mazumder

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors.

Tetsuya Uemura, Toshio Baba

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

2000

Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop.

Tetsuya Uemura, Toshio Baba

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1999

Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit.

Tetsuya Uemura, Pinaki Mazumder

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits.

Toshio Baba, Tetsuya Uemura

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1997

Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits .

Toshio Baba, Tetsuya Uemura

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

1992

3D facial image analysis for human identification.

Takashi Nagamine, Tetsuya Uemura, Isao Masuda

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

1990

Region-based reconstruction of an indoor scene using an integration of active and passive sensing techniques.

Junichi Hoshino, Tetsuya Uemura, Isao Masuda

Proceedings of the Third International Conference on Computer Vision, 1990