Tetsuya Tanabe

According to our database1, Tetsuya Tanabe authored at least 3 papers between 1994 and 1997.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1997
On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM.
IEEE J. Solid State Circuits, 1997

1996
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture.
IEEE J. Solid State Circuits, 1996

1994
A 32-bank 256-Mb DRAM with cache and TAG.
IEEE J. Solid State Circuits, November, 1994


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