Tetsuya Matsumura
According to our database1,
Tetsuya Matsumura
authored at least 25 papers
between 1998 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images.
Proceedings of the IEEE International Conference on Internet of Things and Intelligence Systems, 2023
Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023
Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023
2022
Implementation of Deep Learning-based Hierarchical Object Detection System for High-Resolution Images.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022
2019
Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
Proceedings of the 2019 IEEE International Conference on Internet of Things and Intelligence System, 2019
2018
Automatic Design Environment using High-level Synthesis for Reconfigurable 3D Sound Processor.
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018
Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices.
Proceedings of the IEEE International Conference on Internet of Things and Intelligence System, 2018
2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017
2016
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016
2015
Robotics Auton. Syst., 2015
A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2014
The LSI implementation of a memory based field programmable device for MCU peripherals.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot - 2nd Report: Robot Model Considering Moving Parts and Evaluation of Movable Area by Heights.
Proceedings of the ICINCO 2012 - Proceedings of the 9th International Conference on Informatics in Control, Automation and Robotics, Volume 2, Rome, Italy, 28, 2012
Simultaneous Control of Translational and Rotational Motion for Autonomous Omnidirectional Mobile Robot Considering Shape of the Robot and Movable Area by Heights.
Proceedings of the Intelligent Autonomous Systems 12, 2012
2011
Obstacle Avoidance with Simultaneous Translational and Rotational Motion Control for Autonomous Mobile Robot.
Proceedings of the ICINCO 2011 - Proceedings of the 8th International Conference on Informatics in Control, Automation and Robotics, Volume 2, Noordwijkerhout, The Netherlands, 28, 2011
2002
A 99-mm<sup>2</sup> 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system.
IEEE J. Solid State Circuits, 2002
1999
A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998